2 * QEMU Sparc Sun4m ECC memory controller emulation
4 * Copyright (c) 2007 Robert Reif
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #define DPRINTF(fmt, args...) \
32 do { printf("ECC: " fmt , ##args); } while (0)
34 #define DPRINTF(fmt, args...)
37 /* There are 3 versions of this chip used in SMP sun4m systems:
38 * MCC (version 0, implementation 0) SS-600MP
39 * EMC (version 0, implementation 1) SS-10
40 * SMC (version 0, implementation 2) SS-10SX and SS-20
43 /* Register offsets */
46 #define ECC_FAR0_REG 16
47 #define ECC_FAR1_REG 20
48 #define ECC_DIAG_REG 24
50 /* ECC fault control register */
51 #define ECC_FCR_EE 0x00000001 /* Enable ECC checking */
52 #define ECC_FCR_EI 0x00000010 /* Enable Interrupts on correctable errors */
53 #define ECC_FCR_VER 0x0f000000 /* Version */
54 #define ECC_FCR_IMPL 0xf0000000 /* Implementation */
56 /* ECC fault status register */
57 #define ECC_FSR_CE 0x00000001 /* Correctable error */
58 #define ECC_FSR_BS 0x00000002 /* C2 graphics bad slot access */
59 #define ECC_FSR_TO 0x00000004 /* Timeout on write */
60 #define ECC_FSR_UE 0x00000008 /* Uncorrectable error */
61 #define ECC_FSR_DW 0x000000f0 /* Index of double word in block */
62 #define ECC_FSR_SYND 0x0000ff00 /* Syndrome for correctable error */
63 #define ECC_FSR_ME 0x00010000 /* Multiple errors */
64 #define ECC_FSR_C2ERR 0x00020000 /* C2 graphics error */
66 /* ECC fault address register 0 */
67 #define ECC_FAR0_PADDR 0x0000000f /* PA[32-35] */
68 #define ECC_FAR0_TYPE 0x000000f0 /* Transaction type */
69 #define ECC_FAR0_SIZE 0x00000700 /* Transaction size */
70 #define ECC_FAR0_CACHE 0x00000800 /* Mapped cacheable */
71 #define ECC_FAR0_LOCK 0x00001000 /* Error occurred in attomic cycle */
72 #define ECC_FAR0_BMODE 0x00002000 /* Boot mode */
73 #define ECC_FAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
74 #define ECC_FAR0_S 0x08000000 /* Supervisor mode */
75 #define ECC_FARO_MID 0xf0000000 /* Module ID */
77 /* ECC diagnostic register */
78 #define ECC_DIAG_CBX 0x00000001
79 #define ECC_DIAG_CB0 0x00000002
80 #define ECC_DIAG_CB1 0x00000004
81 #define ECC_DIAG_CB2 0x00000008
82 #define ECC_DIAG_CB4 0x00000010
83 #define ECC_DIAG_CB8 0x00000020
84 #define ECC_DIAG_CB16 0x00000040
85 #define ECC_DIAG_CB32 0x00000080
86 #define ECC_DIAG_DMODE 0x00000c00
89 #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
90 #define ECC_ADDR_MASK (ECC_SIZE - 1)
92 typedef struct ECCState {
93 uint32_t regs[ECC_NREGS];
96 static void ecc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
98 printf("ECC: Unsupported write 0x" TARGET_FMT_plx " %02x\n",
102 static uint32_t ecc_mem_readb(void *opaque, target_phys_addr_t addr)
104 printf("ECC: Unsupported read 0x" TARGET_FMT_plx " 00\n", addr);
108 static void ecc_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
110 printf("ECC: Unsupported write 0x" TARGET_FMT_plx " %04x\n",
114 static uint32_t ecc_mem_readw(void *opaque, target_phys_addr_t addr)
116 printf("ECC: Unsupported read 0x" TARGET_FMT_plx " 0000\n", addr);
120 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
122 ECCState *s = opaque;
124 switch (addr & ECC_ADDR_MASK) {
126 s->regs[0] = (s->regs[0] & (ECC_FCR_VER | ECC_FCR_IMPL)) |
127 (val & ~(ECC_FCR_VER | ECC_FCR_IMPL));
128 DPRINTF("Write fault control %08x\n", val);
132 DPRINTF("Write reg[1] %08x\n", val);
136 DPRINTF("Write fault status %08x\n", val);
140 DPRINTF("Write reg[3] %08x\n", val);
144 DPRINTF("Write fault address 0 %08x\n", val);
148 DPRINTF("Write fault address 1 %08x\n", val);
152 DPRINTF("Write diag %08x\n", val);
156 DPRINTF("Write reg[7] %08x\n", val);
161 static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
163 ECCState *s = opaque;
166 switch (addr & ECC_ADDR_MASK) {
169 DPRINTF("Read enable %08x\n", ret);
173 DPRINTF("Read register[1] %08x\n", ret);
177 DPRINTF("Read fault status %08x\n", ret);
181 DPRINTF("Read reg[3] %08x\n", ret);
185 DPRINTF("Read fault address 0 %08x\n", ret);
189 DPRINTF("Read fault address 1 %08x\n", ret);
193 DPRINTF("Read diag %08x\n", ret);
197 DPRINTF("Read reg[7] %08x\n", ret);
203 static CPUReadMemoryFunc *ecc_mem_read[3] = {
209 static CPUWriteMemoryFunc *ecc_mem_write[3] = {
215 static int ecc_load(QEMUFile *f, void *opaque, int version_id)
217 ECCState *s = opaque;
223 for (i = 0; i < ECC_NREGS; i++)
224 qemu_get_be32s(f, &s->regs[i]);
229 static void ecc_save(QEMUFile *f, void *opaque)
231 ECCState *s = opaque;
234 for (i = 0; i < ECC_NREGS; i++)
235 qemu_put_be32s(f, &s->regs[i]);
238 static void ecc_reset(void *opaque)
240 ECCState *s = opaque;
243 s->regs[ECC_FCR_REG] &= (ECC_FCR_VER | ECC_FCR_IMPL);
245 for (i = 1; i < ECC_NREGS; i++)
249 void * ecc_init(target_phys_addr_t base, uint32_t version)
254 s = qemu_mallocz(sizeof(ECCState));
258 s->regs[0] = version;
260 ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
261 cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
262 register_savevm("ECC", base, 1, ecc_save, ecc_load, s);
263 qemu_register_reset(ecc_reset, s);