2 * QEMU model for the AXIS devboard 88.
4 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
47 static struct nand_state_t nand_state;
48 static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
50 struct nand_state_t *s = opaque;
54 r = nand_getio(s->nand);
55 nand_getpins(s->nand, &rdy);
58 DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
63 nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
65 struct nand_state_t *s = opaque;
68 DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
69 nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
70 nand_setio(s->nand, value);
71 nand_getpins(s->nand, &rdy);
75 static CPUReadMemoryFunc *nand_read[] = {
81 static CPUWriteMemoryFunc *nand_write[] = {
90 unsigned int shiftreg;
99 static void tempsensor_clkedge(struct tempsensor_t *s,
100 unsigned int clk, unsigned int data_in)
102 D(printf("%s clk=%d state=%d sr=%x\n", __func__,
103 clk, s->state, s->shiftreg));
110 /* Output reg is clocked at negedge. */
132 /* Indata is sampled at posedge. */
136 s->shiftreg |= data_in & 1;
138 D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
139 s->regs[0] = s->shiftreg;
143 if ((s->regs[0] & 0xff) == 0) {
144 /* 25 degrees celcius. */
145 s->shiftreg = 0x0b9f;
146 } else if ((s->regs[0] & 0xff) == 0xff) {
147 /* Sensor ID, 0x8100 LM70. */
148 s->shiftreg = 0x8100;
150 printf("Invalid tempsens state %x\n", s->regs[0]);
158 #define RW_PA_DOUT 0x00
159 #define R_PA_DIN 0x01
160 #define RW_PA_OE 0x02
161 #define RW_PD_DOUT 0x10
162 #define R_PD_DIN 0x11
163 #define RW_PD_OE 0x12
165 static struct gpio_state_t
167 struct nand_state_t *nand;
168 struct tempsensor_t tempsensor;
169 uint32_t regs[0x5c / 4];
172 static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
174 struct gpio_state_t *s = opaque;
181 r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
183 /* Encode pins from the nand. */
184 r |= s->nand->rdy << 7;
187 r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
189 /* Encode temp sensor pins. */
190 r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
198 D(printf("%s %x=%x\n", __func__, addr, r));
201 static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
203 struct gpio_state_t *s = opaque;
204 D(printf("%s %x=%x\n", __func__, addr, value));
210 /* Decode nand pins. */
211 s->nand->ale = !!(value & (1 << 6));
212 s->nand->cle = !!(value & (1 << 5));
213 s->nand->ce = !!(value & (1 << 4));
215 s->regs[addr] = value;
219 /* Temp sensor clk. */
220 if ((s->regs[addr] ^ value) & 2)
221 tempsensor_clkedge(&s->tempsensor, !!(value & 2),
223 s->regs[addr] = value;
227 s->regs[addr] = value;
232 static CPUReadMemoryFunc *gpio_read[] = {
237 static CPUWriteMemoryFunc *gpio_write[] = {
242 #define INTMEM_SIZE (128 * 1024)
244 static uint32_t bootstrap_pc;
245 static void main_cpu_reset(void *opaque)
247 CPUState *env = opaque;
250 env->pc = bootstrap_pc;
254 void axisdev88_init (ram_addr_t ram_size,
255 const char *boot_device,
256 const char *kernel_filename, const char *kernel_cmdline,
257 const char *initrd_filename, const char *cpu_model)
262 struct etraxfs_dma_client *eth[2] = {NULL, NULL};
268 ram_addr_t phys_intmem;
271 if (cpu_model == NULL) {
272 cpu_model = "crisv32";
274 env = cpu_init(cpu_model);
275 qemu_register_reset(main_cpu_reset, env);
278 phys_ram = qemu_ram_alloc(ram_size);
279 cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
281 /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
283 phys_intmem = qemu_ram_alloc(INTMEM_SIZE);
284 cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
285 phys_intmem | IO_MEM_RAM);
288 /* Attach a NAND flash to CS1. */
289 nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
290 nand_regs = cpu_register_io_memory(0, nand_read, nand_write, &nand_state);
291 cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
293 gpio_state.nand = &nand_state;
294 gpio_regs = cpu_register_io_memory(0, gpio_read, gpio_write, &gpio_state);
295 cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
298 irq = etraxfs_pic_init(env, 0x3001c000);
301 etraxfs_dmac = etraxfs_dmac_init(env, 0x30000000, 10);
302 for (i = 0; i < 10; i++) {
303 /* On ETRAX, odd numbered channels are inputs. */
304 etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
307 /* Add the two ethernet blocks. */
308 eth[0] = etraxfs_eth_init(&nd_table[0], env, irq + 25, 0x30034000, 1);
310 eth[1] = etraxfs_eth_init(&nd_table[1], env,
311 irq + 26, 0x30036000, 2);
313 /* The DMA Connector block is missing, hardwire things for now. */
314 etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
315 etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1);
317 etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
318 etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
322 etraxfs_timer_init(env, irq + 0x1b, nmi + 1, 0x3001e000);
323 etraxfs_timer_init(env, irq + 0x1b, nmi + 1, 0x3005e000);
325 for (i = 0; i < 4; i++) {
327 etraxfs_ser_init(env, irq + 0x14 + i,
328 serial_hds[i], 0x30026000 + i * 0x2000);
332 if (kernel_filename) {
333 uint64_t entry, high;
336 /* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis
338 kernel_size = load_elf(kernel_filename, -0x80000000LL,
339 &entry, NULL, &high);
340 bootstrap_pc = entry;
341 if (kernel_size < 0) {
342 /* Takes a kimage from the axis devboard SDK. */
343 kernel_size = load_image_targphys(kernel_filename, 0x40004000,
345 bootstrap_pc = 0x40004000;
346 env->regs[9] = 0x40004000 + kernel_size;
348 env->regs[8] = 0x56902387; /* RAM init magic. */
350 if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) {
351 if (kcmdline_len > 256) {
352 fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n");
355 /* Let the kernel know we are modifying the cmdline. */
356 env->regs[10] = 0x87109563;
357 env->regs[11] = 0x40000000;
358 pstrcpy_targphys(env->regs[11], 256, kernel_cmdline);
361 env->pc = bootstrap_pc;
363 printf ("pc =%x\n", env->pc);
364 printf ("ram size =%ld\n", ram_size);
367 QEMUMachine axisdev88_machine = {
368 .name = "axis-dev88",
369 .desc = "AXIS devboard 88",
370 .init = axisdev88_init,