4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #ifdef CONFIG_USER_ONLY
32 #include "qemu-common.h"
33 #include "qemu-char.h"
38 #include "qemu_socket.h"
40 /* XXX: these constants may be independent of the host ones even for Unix */
60 typedef struct GDBState {
61 CPUState *env; /* current CPU */
62 enum RSState state; /* parsing state */
66 uint8_t last_packet[4100];
68 #ifdef CONFIG_USER_ONLY
76 /* By default use no IRQs and no timers while single stepping so as to
77 * make single stepping like an ICE HW step.
79 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
81 #ifdef CONFIG_USER_ONLY
82 /* XXX: This is not thread safe. Do we care? */
83 static int gdbserver_fd = -1;
85 /* XXX: remove this hack. */
86 static GDBState gdbserver_state;
88 static int get_char(GDBState *s)
94 ret = recv(s->fd, &ch, 1, 0);
96 if (errno != EINTR && errno != EAGAIN)
98 } else if (ret == 0) {
108 /* GDB stub state for use by semihosting syscalls. */
109 static GDBState *gdb_syscall_state;
110 static gdb_syscall_complete_cb gdb_current_syscall_cb;
118 /* If gdb is connected when the first semihosting syscall occurs then use
119 remote gdb syscalls. Otherwise use native file IO. */
120 int use_gdb_syscalls(void)
122 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
123 gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
126 return gdb_syscall_mode == GDB_SYS_ENABLED;
129 /* Resume execution. */
130 static inline void gdb_continue(GDBState *s)
132 #ifdef CONFIG_USER_ONLY
133 s->running_state = 1;
139 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
141 #ifdef CONFIG_USER_ONLY
145 ret = send(s->fd, buf, len, 0);
147 if (errno != EINTR && errno != EAGAIN)
155 qemu_chr_write(s->chr, buf, len);
159 static inline int fromhex(int v)
161 if (v >= '0' && v <= '9')
163 else if (v >= 'A' && v <= 'F')
165 else if (v >= 'a' && v <= 'f')
171 static inline int tohex(int v)
179 static void memtohex(char *buf, const uint8_t *mem, int len)
184 for(i = 0; i < len; i++) {
186 *q++ = tohex(c >> 4);
187 *q++ = tohex(c & 0xf);
192 static void hextomem(uint8_t *mem, const char *buf, int len)
196 for(i = 0; i < len; i++) {
197 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
202 /* return -1 if error, 0 if OK */
203 static int put_packet(GDBState *s, char *buf)
209 printf("reply='%s'\n", buf);
219 for(i = 0; i < len; i++) {
223 *(p++) = tohex((csum >> 4) & 0xf);
224 *(p++) = tohex((csum) & 0xf);
226 s->last_packet_len = p - s->last_packet;
227 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
229 #ifdef CONFIG_USER_ONLY
242 #if defined(TARGET_I386)
243 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
246 uint32_t *registers = (uint32_t *)mem_buf;
249 /* This corresponds with amd64_register_info[] in gdb/amd64-tdep.c */
250 uint64_t *registers64 = (uint64_t *)mem_buf;
252 if (env->hflags & HF_CS64_MASK) {
253 registers64[0] = tswap64(env->regs[R_EAX]);
254 registers64[1] = tswap64(env->regs[R_EBX]);
255 registers64[2] = tswap64(env->regs[R_ECX]);
256 registers64[3] = tswap64(env->regs[R_EDX]);
257 registers64[4] = tswap64(env->regs[R_ESI]);
258 registers64[5] = tswap64(env->regs[R_EDI]);
259 registers64[6] = tswap64(env->regs[R_EBP]);
260 registers64[7] = tswap64(env->regs[R_ESP]);
261 for(i = 8; i < 16; i++) {
262 registers64[i] = tswap64(env->regs[i]);
264 registers64[16] = tswap64(env->eip);
266 registers = (uint32_t *)®isters64[17];
267 registers[0] = tswap32(env->eflags);
268 registers[1] = tswap32(env->segs[R_CS].selector);
269 registers[2] = tswap32(env->segs[R_SS].selector);
270 registers[3] = tswap32(env->segs[R_DS].selector);
271 registers[4] = tswap32(env->segs[R_ES].selector);
272 registers[5] = tswap32(env->segs[R_FS].selector);
273 registers[6] = tswap32(env->segs[R_GS].selector);
274 /* XXX: convert floats */
275 for(i = 0; i < 8; i++) {
276 memcpy(mem_buf + 16 * 8 + 7 * 4 + i * 10, &env->fpregs[i], 10);
278 registers[27] = tswap32(env->fpuc); /* fctrl */
279 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
280 registers[28] = tswap32(fpus); /* fstat */
281 registers[29] = 0; /* ftag */
282 registers[30] = 0; /* fiseg */
283 registers[31] = 0; /* fioff */
284 registers[32] = 0; /* foseg */
285 registers[33] = 0; /* fooff */
286 registers[34] = 0; /* fop */
287 for(i = 0; i < 16; i++) {
288 memcpy(mem_buf + 16 * 8 + 35 * 4 + i * 16, &env->xmm_regs[i], 16);
290 registers[99] = tswap32(env->mxcsr);
292 return 8 * 17 + 4 * 7 + 10 * 8 + 4 * 8 + 16 * 16 + 4;
296 for(i = 0; i < 8; i++) {
297 registers[i] = env->regs[i];
299 registers[8] = env->eip;
300 registers[9] = env->eflags;
301 registers[10] = env->segs[R_CS].selector;
302 registers[11] = env->segs[R_SS].selector;
303 registers[12] = env->segs[R_DS].selector;
304 registers[13] = env->segs[R_ES].selector;
305 registers[14] = env->segs[R_FS].selector;
306 registers[15] = env->segs[R_GS].selector;
307 /* XXX: convert floats */
308 for(i = 0; i < 8; i++) {
309 memcpy(mem_buf + 16 * 4 + i * 10, &env->fpregs[i], 10);
311 registers[36] = env->fpuc;
312 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
313 registers[37] = fpus;
314 registers[38] = 0; /* XXX: convert tags */
315 registers[39] = 0; /* fiseg */
316 registers[40] = 0; /* fioff */
317 registers[41] = 0; /* foseg */
318 registers[42] = 0; /* fooff */
319 registers[43] = 0; /* fop */
321 for(i = 0; i < 16; i++)
322 tswapls(®isters[i]);
323 for(i = 36; i < 44; i++)
324 tswapls(®isters[i]);
328 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
330 uint32_t *registers = (uint32_t *)mem_buf;
333 for(i = 0; i < 8; i++) {
334 env->regs[i] = tswapl(registers[i]);
336 env->eip = tswapl(registers[8]);
337 env->eflags = tswapl(registers[9]);
338 #if defined(CONFIG_USER_ONLY)
339 #define LOAD_SEG(index, sreg)\
340 if (tswapl(registers[index]) != env->segs[sreg].selector)\
341 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
351 #elif defined (TARGET_PPC)
352 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
354 uint32_t *registers = (uint32_t *)mem_buf, tmp;
358 for(i = 0; i < 32; i++) {
359 registers[i] = tswapl(env->gpr[i]);
362 for (i = 0; i < 32; i++) {
363 registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
364 registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
366 /* nip, msr, ccr, lnk, ctr, xer, mq */
367 registers[96] = tswapl(env->nip);
368 registers[97] = tswapl(env->msr);
370 for (i = 0; i < 8; i++)
371 tmp |= env->crf[i] << (32 - ((i + 1) * 4));
372 registers[98] = tswapl(tmp);
373 registers[99] = tswapl(env->lr);
374 registers[100] = tswapl(env->ctr);
375 registers[101] = tswapl(ppc_load_xer(env));
381 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
383 uint32_t *registers = (uint32_t *)mem_buf;
387 for (i = 0; i < 32; i++) {
388 env->gpr[i] = tswapl(registers[i]);
391 for (i = 0; i < 32; i++) {
392 *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
393 *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
395 /* nip, msr, ccr, lnk, ctr, xer, mq */
396 env->nip = tswapl(registers[96]);
397 ppc_store_msr(env, tswapl(registers[97]));
398 registers[98] = tswapl(registers[98]);
399 for (i = 0; i < 8; i++)
400 env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
401 env->lr = tswapl(registers[99]);
402 env->ctr = tswapl(registers[100]);
403 ppc_store_xer(env, tswapl(registers[101]));
405 #elif defined (TARGET_SPARC)
406 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
408 target_ulong *registers = (target_ulong *)mem_buf;
412 for(i = 0; i < 8; i++) {
413 registers[i] = tswapl(env->gregs[i]);
415 /* fill in register window */
416 for(i = 0; i < 24; i++) {
417 registers[i + 8] = tswapl(env->regwptr[i]);
419 #ifndef TARGET_SPARC64
421 for (i = 0; i < 32; i++) {
422 registers[i + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
424 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
425 registers[64] = tswapl(env->y);
430 registers[65] = tswapl(tmp);
432 registers[66] = tswapl(env->wim);
433 registers[67] = tswapl(env->tbr);
434 registers[68] = tswapl(env->pc);
435 registers[69] = tswapl(env->npc);
436 registers[70] = tswapl(env->fsr);
437 registers[71] = 0; /* csr */
439 return 73 * sizeof(target_ulong);
442 for (i = 0; i < 64; i += 2) {
445 tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
446 tmp |= *(uint32_t *)&env->fpr[i + 1];
447 registers[i / 2 + 32] = tswap64(tmp);
449 registers[64] = tswapl(env->pc);
450 registers[65] = tswapl(env->npc);
451 registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
452 ((env->asi & 0xff) << 24) |
453 ((env->pstate & 0xfff) << 8) |
455 registers[67] = tswapl(env->fsr);
456 registers[68] = tswapl(env->fprs);
457 registers[69] = tswapl(env->y);
458 return 70 * sizeof(target_ulong);
462 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
464 target_ulong *registers = (target_ulong *)mem_buf;
468 for(i = 0; i < 7; i++) {
469 env->gregs[i] = tswapl(registers[i]);
471 /* fill in register window */
472 for(i = 0; i < 24; i++) {
473 env->regwptr[i] = tswapl(registers[i + 8]);
475 #ifndef TARGET_SPARC64
477 for (i = 0; i < 32; i++) {
478 *((uint32_t *)&env->fpr[i]) = tswapl(registers[i + 32]);
480 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
481 env->y = tswapl(registers[64]);
482 PUT_PSR(env, tswapl(registers[65]));
483 env->wim = tswapl(registers[66]);
484 env->tbr = tswapl(registers[67]);
485 env->pc = tswapl(registers[68]);
486 env->npc = tswapl(registers[69]);
487 env->fsr = tswapl(registers[70]);
489 for (i = 0; i < 64; i += 2) {
492 tmp = tswap64(registers[i / 2 + 32]);
493 *((uint32_t *)&env->fpr[i]) = tmp >> 32;
494 *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
496 env->pc = tswapl(registers[64]);
497 env->npc = tswapl(registers[65]);
499 uint64_t tmp = tswapl(registers[66]);
501 PUT_CCR(env, tmp >> 32);
502 env->asi = (tmp >> 24) & 0xff;
503 env->pstate = (tmp >> 8) & 0xfff;
504 PUT_CWP64(env, tmp & 0xff);
506 env->fsr = tswapl(registers[67]);
507 env->fprs = tswapl(registers[68]);
508 env->y = tswapl(registers[69]);
511 #elif defined (TARGET_ARM)
512 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
518 /* 16 core integer registers (4 bytes each). */
519 for (i = 0; i < 16; i++)
521 *(uint32_t *)ptr = tswapl(env->regs[i]);
524 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
525 Not yet implemented. */
526 memset (ptr, 0, 8 * 12 + 4);
528 /* CPSR (4 bytes). */
529 *(uint32_t *)ptr = tswapl (cpsr_read(env));
532 return ptr - mem_buf;
535 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
541 /* Core integer registers. */
542 for (i = 0; i < 16; i++)
544 env->regs[i] = tswapl(*(uint32_t *)ptr);
547 /* Ignore FPA regs and scr. */
549 cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
551 #elif defined (TARGET_M68K)
552 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
560 for (i = 0; i < 8; i++) {
561 *(uint32_t *)ptr = tswapl(env->dregs[i]);
565 for (i = 0; i < 8; i++) {
566 *(uint32_t *)ptr = tswapl(env->aregs[i]);
569 *(uint32_t *)ptr = tswapl(env->sr);
571 *(uint32_t *)ptr = tswapl(env->pc);
573 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
574 ColdFire has 8-bit double precision registers. */
575 for (i = 0; i < 8; i++) {
577 *(uint32_t *)ptr = tswap32(u.l.upper);
578 *(uint32_t *)ptr = tswap32(u.l.lower);
580 /* FP control regs (not implemented). */
581 memset (ptr, 0, 3 * 4);
584 return ptr - mem_buf;
587 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
595 for (i = 0; i < 8; i++) {
596 env->dregs[i] = tswapl(*(uint32_t *)ptr);
600 for (i = 0; i < 8; i++) {
601 env->aregs[i] = tswapl(*(uint32_t *)ptr);
604 env->sr = tswapl(*(uint32_t *)ptr);
606 env->pc = tswapl(*(uint32_t *)ptr);
608 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
609 ColdFire has 8-bit double precision registers. */
610 for (i = 0; i < 8; i++) {
611 u.l.upper = tswap32(*(uint32_t *)ptr);
612 u.l.lower = tswap32(*(uint32_t *)ptr);
615 /* FP control regs (not implemented). */
618 #elif defined (TARGET_MIPS)
619 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
625 for (i = 0; i < 32; i++)
627 *(target_ulong *)ptr = tswapl(env->gpr[env->current_tc][i]);
628 ptr += sizeof(target_ulong);
631 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
632 ptr += sizeof(target_ulong);
634 *(target_ulong *)ptr = tswapl(env->LO[env->current_tc][0]);
635 ptr += sizeof(target_ulong);
637 *(target_ulong *)ptr = tswapl(env->HI[env->current_tc][0]);
638 ptr += sizeof(target_ulong);
640 *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
641 ptr += sizeof(target_ulong);
643 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
644 ptr += sizeof(target_ulong);
646 *(target_ulong *)ptr = tswapl(env->PC[env->current_tc]);
647 ptr += sizeof(target_ulong);
649 if (env->CP0_Config1 & (1 << CP0C1_FP))
651 for (i = 0; i < 32; i++)
653 if (env->CP0_Status & (1 << CP0St_FR))
654 *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
656 *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
657 ptr += sizeof(target_ulong);
660 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
661 ptr += sizeof(target_ulong);
663 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
664 ptr += sizeof(target_ulong);
667 /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
668 *(target_ulong *)ptr = 0;
669 ptr += sizeof(target_ulong);
671 /* Registers for embedded use, we just pad them. */
672 for (i = 0; i < 16; i++)
674 *(target_ulong *)ptr = 0;
675 ptr += sizeof(target_ulong);
679 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
680 ptr += sizeof(target_ulong);
682 return ptr - mem_buf;
685 /* convert MIPS rounding mode in FCR31 to IEEE library */
686 static unsigned int ieee_rm[] =
688 float_round_nearest_even,
693 #define RESTORE_ROUNDING_MODE \
694 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
696 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
702 for (i = 0; i < 32; i++)
704 env->gpr[env->current_tc][i] = tswapl(*(target_ulong *)ptr);
705 ptr += sizeof(target_ulong);
708 env->CP0_Status = tswapl(*(target_ulong *)ptr);
709 ptr += sizeof(target_ulong);
711 env->LO[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
712 ptr += sizeof(target_ulong);
714 env->HI[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
715 ptr += sizeof(target_ulong);
717 env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
718 ptr += sizeof(target_ulong);
720 env->CP0_Cause = tswapl(*(target_ulong *)ptr);
721 ptr += sizeof(target_ulong);
723 env->PC[env->current_tc] = tswapl(*(target_ulong *)ptr);
724 ptr += sizeof(target_ulong);
726 if (env->CP0_Config1 & (1 << CP0C1_FP))
728 for (i = 0; i < 32; i++)
730 if (env->CP0_Status & (1 << CP0St_FR))
731 env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
733 env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
734 ptr += sizeof(target_ulong);
737 env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
738 ptr += sizeof(target_ulong);
740 /* The remaining registers are assumed to be read-only. */
742 /* set rounding mode */
743 RESTORE_ROUNDING_MODE;
745 #ifndef CONFIG_SOFTFLOAT
746 /* no floating point exception for native float */
747 SET_FP_ENABLE(env->fcr31, 0);
751 #elif defined (TARGET_SH4)
753 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
755 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
757 uint32_t *ptr = (uint32_t *)mem_buf;
760 #define SAVE(x) *ptr++=tswapl(x)
761 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
762 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
764 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
766 for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
776 for (i = 0; i < 16; i++)
777 SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
780 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
781 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
782 return ((uint8_t *)ptr - mem_buf);
785 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
787 uint32_t *ptr = (uint32_t *)mem_buf;
790 #define LOAD(x) (x)=*ptr++;
791 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
792 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
794 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
796 for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
806 for (i = 0; i < 16; i++)
807 LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
810 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
811 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
813 #elif defined (TARGET_CRIS)
815 static int cris_save_32 (unsigned char *d, uint32_t value)
818 *d++ = (value >>= 8);
819 *d++ = (value >>= 8);
820 *d++ = (value >>= 8);
823 static int cris_save_16 (unsigned char *d, uint32_t value)
826 *d++ = (value >>= 8);
829 static int cris_save_8 (unsigned char *d, uint32_t value)
835 /* FIXME: this will bug on archs not supporting unaligned word accesses. */
836 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
838 uint8_t *ptr = mem_buf;
842 for (i = 0; i < 16; i++)
843 ptr += cris_save_32 (ptr, env->regs[i]);
845 srs = env->pregs[PR_SRS];
847 ptr += cris_save_8 (ptr, env->pregs[0]);
848 ptr += cris_save_8 (ptr, env->pregs[1]);
849 ptr += cris_save_32 (ptr, env->pregs[2]);
850 ptr += cris_save_8 (ptr, srs);
851 ptr += cris_save_16 (ptr, env->pregs[4]);
853 for (i = 5; i < 16; i++)
854 ptr += cris_save_32 (ptr, env->pregs[i]);
856 ptr += cris_save_32 (ptr, env->pc);
858 for (i = 0; i < 16; i++)
859 ptr += cris_save_32 (ptr, env->sregs[srs][i]);
861 return ((uint8_t *)ptr - mem_buf);
864 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
866 uint32_t *ptr = (uint32_t *)mem_buf;
869 #define LOAD(x) (x)=*ptr++;
870 for (i = 0; i < 16; i++) LOAD(env->regs[i]);
874 static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
879 static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
885 static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
888 int ch, reg_size, type;
890 uint8_t mem_buf[4096];
892 target_ulong addr, len;
895 printf("command='%s'\n", line_buf);
901 /* TODO: Make this return the correct value for user-mode. */
902 snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
907 addr = strtoull(p, (char **)&p, 16);
908 #if defined(TARGET_I386)
910 #elif defined (TARGET_PPC)
912 #elif defined (TARGET_SPARC)
915 #elif defined (TARGET_ARM)
916 env->regs[15] = addr;
917 #elif defined (TARGET_SH4)
919 #elif defined (TARGET_MIPS)
920 env->PC[env->current_tc] = addr;
921 #elif defined (TARGET_CRIS)
929 addr = strtoull(p, (char **)&p, 16);
930 #if defined(TARGET_I386)
932 #elif defined (TARGET_PPC)
934 #elif defined (TARGET_SPARC)
937 #elif defined (TARGET_ARM)
938 env->regs[15] = addr;
939 #elif defined (TARGET_SH4)
941 #elif defined (TARGET_MIPS)
942 env->PC[env->current_tc] = addr;
943 #elif defined (TARGET_CRIS)
947 cpu_single_step(env, sstep_flags);
955 ret = strtoull(p, (char **)&p, 16);
958 err = strtoull(p, (char **)&p, 16);
965 if (gdb_current_syscall_cb)
966 gdb_current_syscall_cb(s->env, ret, err);
968 put_packet(s, "T02");
975 reg_size = cpu_gdb_read_registers(env, mem_buf);
976 memtohex(buf, mem_buf, reg_size);
980 registers = (void *)mem_buf;
982 hextomem((uint8_t *)registers, p, len);
983 cpu_gdb_write_registers(env, mem_buf, len);
987 addr = strtoull(p, (char **)&p, 16);
990 len = strtoull(p, NULL, 16);
991 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
992 put_packet (s, "E14");
994 memtohex(buf, mem_buf, len);
999 addr = strtoull(p, (char **)&p, 16);
1002 len = strtoull(p, (char **)&p, 16);
1005 hextomem(mem_buf, p, len);
1006 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
1007 put_packet(s, "E14");
1009 put_packet(s, "OK");
1012 type = strtoul(p, (char **)&p, 16);
1015 addr = strtoull(p, (char **)&p, 16);
1018 len = strtoull(p, (char **)&p, 16);
1019 if (type == 0 || type == 1) {
1020 if (cpu_breakpoint_insert(env, addr) < 0)
1021 goto breakpoint_error;
1022 put_packet(s, "OK");
1023 #ifndef CONFIG_USER_ONLY
1024 } else if (type == 2) {
1025 if (cpu_watchpoint_insert(env, addr) < 0)
1026 goto breakpoint_error;
1027 put_packet(s, "OK");
1031 put_packet(s, "E22");
1035 type = strtoul(p, (char **)&p, 16);
1038 addr = strtoull(p, (char **)&p, 16);
1041 len = strtoull(p, (char **)&p, 16);
1042 if (type == 0 || type == 1) {
1043 cpu_breakpoint_remove(env, addr);
1044 put_packet(s, "OK");
1045 #ifndef CONFIG_USER_ONLY
1046 } else if (type == 2) {
1047 cpu_watchpoint_remove(env, addr);
1048 put_packet(s, "OK");
1051 goto breakpoint_error;
1056 /* parse any 'q' packets here */
1057 if (!strcmp(p,"qemu.sstepbits")) {
1058 /* Query Breakpoint bit definitions */
1059 sprintf(buf,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1065 } else if (strncmp(p,"qemu.sstep",10) == 0) {
1066 /* Display or change the sstep_flags */
1069 /* Display current setting */
1070 sprintf(buf,"0x%x", sstep_flags);
1075 type = strtoul(p, (char **)&p, 16);
1077 put_packet(s, "OK");
1080 #ifdef CONFIG_LINUX_USER
1081 else if (strncmp(p, "Offsets", 7) == 0) {
1082 TaskState *ts = env->opaque;
1085 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1086 ";Bss=" TARGET_ABI_FMT_lx,
1087 ts->info->code_offset,
1088 ts->info->data_offset,
1089 ts->info->data_offset);
1096 /* put empty packet */
1104 extern void tb_flush(CPUState *env);
1106 #ifndef CONFIG_USER_ONLY
1107 static void gdb_vm_stopped(void *opaque, int reason)
1109 GDBState *s = opaque;
1113 if (s->state == RS_SYSCALL)
1116 /* disable single step if it was enable */
1117 cpu_single_step(s->env, 0);
1119 if (reason == EXCP_DEBUG) {
1120 if (s->env->watchpoint_hit) {
1121 snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
1123 s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
1125 s->env->watchpoint_hit = 0;
1130 } else if (reason == EXCP_INTERRUPT) {
1135 snprintf(buf, sizeof(buf), "S%02x", ret);
1140 /* Send a gdb syscall request.
1141 This accepts limited printf-style format specifiers, specifically:
1142 %x - target_ulong argument printed in hex.
1143 %lx - 64-bit argument printed in hex.
1144 %s - string pointer (target_ulong) and length (int) pair. */
1145 void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...)
1154 s = gdb_syscall_state;
1157 gdb_current_syscall_cb = cb;
1158 s->state = RS_SYSCALL;
1159 #ifndef CONFIG_USER_ONLY
1160 vm_stop(EXCP_DEBUG);
1171 addr = va_arg(va, target_ulong);
1172 p += sprintf(p, TARGET_FMT_lx, addr);
1175 if (*(fmt++) != 'x')
1177 i64 = va_arg(va, uint64_t);
1178 p += sprintf(p, "%" PRIx64, i64);
1181 addr = va_arg(va, target_ulong);
1182 p += sprintf(p, TARGET_FMT_lx "/%x", addr, va_arg(va, int));
1186 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1197 #ifdef CONFIG_USER_ONLY
1198 gdb_handlesig(s->env, 0);
1200 cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
1204 static void gdb_read_byte(GDBState *s, int ch)
1206 CPUState *env = s->env;
1210 #ifndef CONFIG_USER_ONLY
1211 if (s->last_packet_len) {
1212 /* Waiting for a response to the last packet. If we see the start
1213 of a new command then abandon the previous response. */
1216 printf("Got NACK, retransmitting\n");
1218 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
1222 printf("Got ACK\n");
1224 printf("Got '%c' when expecting ACK/NACK\n", ch);
1226 if (ch == '+' || ch == '$')
1227 s->last_packet_len = 0;
1232 /* when the CPU is running, we cannot do anything except stop
1233 it when receiving a char */
1234 vm_stop(EXCP_INTERRUPT);
1241 s->line_buf_index = 0;
1242 s->state = RS_GETLINE;
1247 s->state = RS_CHKSUM1;
1248 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1251 s->line_buf[s->line_buf_index++] = ch;
1255 s->line_buf[s->line_buf_index] = '\0';
1256 s->line_csum = fromhex(ch) << 4;
1257 s->state = RS_CHKSUM2;
1260 s->line_csum |= fromhex(ch);
1262 for(i = 0; i < s->line_buf_index; i++) {
1263 csum += s->line_buf[i];
1265 if (s->line_csum != (csum & 0xff)) {
1267 put_buffer(s, &reply, 1);
1271 put_buffer(s, &reply, 1);
1272 s->state = gdb_handle_packet(s, env, s->line_buf);
1281 #ifdef CONFIG_USER_ONLY
1283 gdb_handlesig (CPUState *env, int sig)
1289 if (gdbserver_fd < 0)
1292 s = &gdbserver_state;
1294 /* disable single step if it was enabled */
1295 cpu_single_step(env, 0);
1300 snprintf(buf, sizeof(buf), "S%02x", sig);
1306 s->running_state = 0;
1307 while (s->running_state == 0) {
1308 n = read (s->fd, buf, 256);
1313 for (i = 0; i < n; i++)
1314 gdb_read_byte (s, buf[i]);
1316 else if (n == 0 || errno != EAGAIN)
1318 /* XXX: Connection closed. Should probably wait for annother
1319 connection before continuing. */
1326 /* Tell the remote gdb that the process has exited. */
1327 void gdb_exit(CPUState *env, int code)
1332 if (gdbserver_fd < 0)
1335 s = &gdbserver_state;
1337 snprintf(buf, sizeof(buf), "W%02x", code);
1342 static void gdb_accept(void *opaque)
1345 struct sockaddr_in sockaddr;
1350 len = sizeof(sockaddr);
1351 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1352 if (fd < 0 && errno != EINTR) {
1355 } else if (fd >= 0) {
1360 /* set short latency */
1362 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
1364 s = &gdbserver_state;
1365 memset (s, 0, sizeof (GDBState));
1366 s->env = first_cpu; /* XXX: allow to change CPU */
1369 gdb_syscall_state = s;
1371 fcntl(fd, F_SETFL, O_NONBLOCK);
1374 static int gdbserver_open(int port)
1376 struct sockaddr_in sockaddr;
1379 fd = socket(PF_INET, SOCK_STREAM, 0);
1385 /* allow fast reuse */
1387 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
1389 sockaddr.sin_family = AF_INET;
1390 sockaddr.sin_port = htons(port);
1391 sockaddr.sin_addr.s_addr = 0;
1392 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1397 ret = listen(fd, 0);
1405 int gdbserver_start(int port)
1407 gdbserver_fd = gdbserver_open(port);
1408 if (gdbserver_fd < 0)
1410 /* accept connections */
1415 static int gdb_chr_can_receive(void *opaque)
1420 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
1422 GDBState *s = opaque;
1425 for (i = 0; i < size; i++) {
1426 gdb_read_byte(s, buf[i]);
1430 static void gdb_chr_event(void *opaque, int event)
1433 case CHR_EVENT_RESET:
1434 vm_stop(EXCP_INTERRUPT);
1435 gdb_syscall_state = opaque;
1442 int gdbserver_start(const char *port)
1445 char gdbstub_port_name[128];
1448 CharDriverState *chr;
1450 if (!port || !*port)
1453 port_num = strtol(port, &p, 10);
1455 /* A numeric value is interpreted as a port number. */
1456 snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
1457 "tcp::%d,nowait,nodelay,server", port_num);
1458 port = gdbstub_port_name;
1461 chr = qemu_chr_open(port);
1465 s = qemu_mallocz(sizeof(GDBState));
1469 s->env = first_cpu; /* XXX: allow to change CPU */
1471 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
1473 qemu_add_vm_stop_handler(gdb_vm_stopped, s);