2 * Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
4 * (c) Copyright 1996 - 2001 Gary Henderson (gary.henderson@ntlworld.com) and
5 * Jerremy Koot (jkoot@snes9x.com)
7 * Super FX C emulator code
8 * (c) Copyright 1997 - 1999 Ivar (ivar@snes9x.com) and
10 * Super FX assembler emulator code (c) Copyright 1998 zsKnight and _Demo_.
12 * DSP1 emulator code (c) Copyright 1998 Ivar, _Demo_ and Gary Henderson.
13 * C4 asm and some C emulation code (c) Copyright 2000 zsKnight and _Demo_.
14 * C4 C code (c) Copyright 2001 Gary Henderson (gary.henderson@ntlworld.com).
16 * DOS port code contains the works of other authors. See headers in
19 * Snes9x homepage: http://www.snes9x.com
21 * Permission to use, copy, modify and distribute Snes9x in both binary and
22 * source form, for non-commercial purposes, is hereby granted without fee,
23 * providing that this license information and copyright notice appear with
24 * all copies and any derived work.
26 * This software is provided 'as-is', without any express or implied
27 * warranty. In no event shall the authors be held liable for any damages
28 * arising from the use of this software.
30 * Snes9x is freeware for PERSONAL USE only. Commercial users should
31 * seek permission of the copyright holders first. Commercial use includes
32 * charging money for Snes9x or software derived from Snes9x.
34 * The copyright holders request that bug fixes and improvements to the code
35 * should be forwarded to them so everyone can benefit from the modifications
38 * Super NES and Super Nintendo Entertainment System are trademarks of
39 * Nintendo Co., Limited and its subsidiary companies.
41 #define FX_DO_ROMBUFFER
48 extern struct FxRegs_s GSU;
49 int gsu_bank [512] = {0};
51 /* Set this define if you wish the plot instruction to check for y-pos limits */
52 /* (I don't think it's nessecary) */
57 * rn = a GSU register (r0-r15)
58 * #n = 4 bit immediate value
59 * #pp = 8 bit immediate value
60 * (yy) = 8 bit word address (0x0000 - 0x01fe)
61 * #xx = 16 bit immediate value
62 * (xx) = 16 bit address (0x0000 - 0xffff)
66 /* 00 - stop - stop GSU execution (and maybe generate an IRQ) */
71 GSU.vInstCount = GSU.vCounter;
73 /* Check if we need to generate an IRQ */
74 if(!(GSU.pvRegisters[GSU_CFGR] & 0x80))
77 GSU.vPlotOptionReg = 0;
83 /* 01 - nop - no operation */
84 static void fx_nop() { CLRFLAGS; R15++; }
86 extern void fx_flushCache();
88 /* 02 - cache - reintialize GSU cache */
89 static void fx_cache()
91 uint32 c = R15 & 0xfff0;
92 if(GSU.vCacheBaseReg != c || !GSU.bCacheActive)
95 GSU.vCacheBaseReg = c;
96 GSU.bCacheActive = TRUE;
100 uint8 const* t = &ROM(c);
101 memcpy(GSU.pvCache,t,512);
107 uint32 i = 0x10000 - c;
110 memcpy(GSU.pvCache,t1,i);
111 memcpy(&GSU.pvCache[i],t2,512-i);
119 /* 03 - lsr - logic shift right */
123 GSU.vCarry = SREG & 1;
124 v = USEX16(SREG) >> 1;
132 /* 04 - rol - rotate left */
135 uint32 v = (SREG << 1) + GSU.vCarry;
136 GSU.vCarry = (SREG >> 15) & 1;
144 /* 05 - bra - branch always */
145 static void fx_bra() { uint8 v = PIPE; R15++; FETCHPIPE; R15 += SEX8(v); }
147 /* Branch on condition */
148 #define BRA_COND(cond) uint8 v = PIPE; R15++; FETCHPIPE; if(cond) R15 += SEX8(v); else R15++;
150 #define TEST_S (GSU.vSign & 0x8000)
151 #define TEST_Z (USEX16(GSU.vZero) == 0)
152 #define TEST_OV (GSU.vOverflow >= 0x8000 || GSU.vOverflow < -0x8000)
153 #define TEST_CY (GSU.vCarry & 1)
155 /* 06 - blt - branch on less than */
156 static void fx_blt() { BRA_COND( (TEST_S!=0) != (TEST_OV!=0) ); }
158 /* 07 - bge - branch on greater or equals */
159 static void fx_bge() { BRA_COND( (TEST_S!=0) == (TEST_OV!=0)); }
161 /* 08 - bne - branch on not equal */
162 static void fx_bne() { BRA_COND( !TEST_Z ); }
164 /* 09 - beq - branch on equal */
165 static void fx_beq() { BRA_COND( TEST_Z ); }
167 /* 0a - bpl - branch on plus */
168 static void fx_bpl() { BRA_COND( !TEST_S ); }
170 /* 0b - bmi - branch on minus */
171 static void fx_bmi() { BRA_COND( TEST_S ); }
173 /* 0c - bcc - branch on carry clear */
174 static void fx_bcc() { BRA_COND( !TEST_CY ); }
176 /* 0d - bcs - branch on carry set */
177 static void fx_bcs() { BRA_COND( TEST_CY ); }
179 /* 0e - bvc - branch on overflow clear */
180 static void fx_bvc() { BRA_COND( !TEST_OV ); }
182 /* 0f - bvs - branch on overflow set */
183 static void fx_bvs() { BRA_COND( TEST_OV ); }
185 /* 10-1f - to rn - set register n as destination register */
186 /* 10-1f(B) - move rn - move one register to another (if B flag is set) */
188 if(TF(B)) { GSU.avReg[(reg)] = SREG; CLRFLAGS; } \
189 else { GSU.pvDreg = &GSU.avReg[reg]; } R15++;
190 #define FX_TO_R14(reg) \
191 if(TF(B)) { GSU.avReg[(reg)] = SREG; CLRFLAGS; READR14; } \
192 else { GSU.pvDreg = &GSU.avReg[reg]; } R15++;
193 #define FX_TO_R15(reg) \
194 if(TF(B)) { GSU.avReg[(reg)] = SREG; CLRFLAGS; } \
195 else { GSU.pvDreg = &GSU.avReg[reg]; R15++; }
196 static void fx_to_r0() { FX_TO(0); }
197 static void fx_to_r1() { FX_TO(1); }
198 static void fx_to_r2() { FX_TO(2); }
199 static void fx_to_r3() { FX_TO(3); }
200 static void fx_to_r4() { FX_TO(4); }
201 static void fx_to_r5() { FX_TO(5); }
202 static void fx_to_r6() { FX_TO(6); }
203 static void fx_to_r7() { FX_TO(7); }
204 static void fx_to_r8() { FX_TO(8); }
205 static void fx_to_r9() { FX_TO(9); }
206 static void fx_to_r10() { FX_TO(10); }
207 static void fx_to_r11() { FX_TO(11); }
208 static void fx_to_r12() { FX_TO(12); }
209 static void fx_to_r13() { FX_TO(13); }
210 static void fx_to_r14() { FX_TO_R14(14); }
211 static void fx_to_r15() { FX_TO_R15(15); }
213 /* 20-2f - to rn - set register n as source and destination register */
214 #define FX_WITH(reg) SF(B); GSU.pvSreg = GSU.pvDreg = &GSU.avReg[reg]; R15++;
215 static void fx_with_r0() { FX_WITH(0); }
216 static void fx_with_r1() { FX_WITH(1); }
217 static void fx_with_r2() { FX_WITH(2); }
218 static void fx_with_r3() { FX_WITH(3); }
219 static void fx_with_r4() { FX_WITH(4); }
220 static void fx_with_r5() { FX_WITH(5); }
221 static void fx_with_r6() { FX_WITH(6); }
222 static void fx_with_r7() { FX_WITH(7); }
223 static void fx_with_r8() { FX_WITH(8); }
224 static void fx_with_r9() { FX_WITH(9); }
225 static void fx_with_r10() { FX_WITH(10); }
226 static void fx_with_r11() { FX_WITH(11); }
227 static void fx_with_r12() { FX_WITH(12); }
228 static void fx_with_r13() { FX_WITH(13); }
229 static void fx_with_r14() { FX_WITH(14); }
230 static void fx_with_r15() { FX_WITH(15); }
232 /* 30-3b - stw (rn) - store word */
233 #define FX_STW(reg) \
234 GSU.vLastRamAdr = GSU.avReg[reg]; \
235 RAM(GSU.avReg[reg]) = (uint8)SREG; \
236 RAM(GSU.avReg[reg]^1) = (uint8)(SREG>>8); \
238 static void fx_stw_r0() { FX_STW(0); }
239 static void fx_stw_r1() { FX_STW(1); }
240 static void fx_stw_r2() { FX_STW(2); }
241 static void fx_stw_r3() { FX_STW(3); }
242 static void fx_stw_r4() { FX_STW(4); }
243 static void fx_stw_r5() { FX_STW(5); }
244 static void fx_stw_r6() { FX_STW(6); }
245 static void fx_stw_r7() { FX_STW(7); }
246 static void fx_stw_r8() { FX_STW(8); }
247 static void fx_stw_r9() { FX_STW(9); }
248 static void fx_stw_r10() { FX_STW(10); }
249 static void fx_stw_r11() { FX_STW(11); }
251 /* 30-3b(ALT1) - stb (rn) - store byte */
252 #define FX_STB(reg) \
253 GSU.vLastRamAdr = GSU.avReg[reg]; \
254 RAM(GSU.avReg[reg]) = (uint8)SREG; \
256 static void fx_stb_r0() { FX_STB(0); }
257 static void fx_stb_r1() { FX_STB(1); }
258 static void fx_stb_r2() { FX_STB(2); }
259 static void fx_stb_r3() { FX_STB(3); }
260 static void fx_stb_r4() { FX_STB(4); }
261 static void fx_stb_r5() { FX_STB(5); }
262 static void fx_stb_r6() { FX_STB(6); }
263 static void fx_stb_r7() { FX_STB(7); }
264 static void fx_stb_r8() { FX_STB(8); }
265 static void fx_stb_r9() { FX_STB(9); }
266 static void fx_stb_r10() { FX_STB(10); }
267 static void fx_stb_r11() { FX_STB(11); }
269 /* 3c - loop - decrement loop counter, and branch on not zero */
270 static void fx_loop()
272 GSU.vSign = GSU.vZero = --R12;
273 if( (uint16) R12 != 0 )
281 /* 3d - alt1 - set alt1 mode */
282 static void fx_alt1() { SF(ALT1); CF(B); R15++; }
284 /* 3e - alt2 - set alt2 mode */
285 static void fx_alt2() { SF(ALT2); CF(B); R15++; }
287 /* 3f - alt3 - set alt3 mode */
288 static void fx_alt3() { SF(ALT1); SF(ALT2); CF(B); R15++; }
290 /* 40-4b - ldw (rn) - load word from RAM */
291 #define FX_LDW(reg) uint32 v; \
292 GSU.vLastRamAdr = GSU.avReg[reg]; \
293 v = (uint32)RAM(GSU.avReg[reg]); \
294 v |= ((uint32)RAM(GSU.avReg[reg]^1))<<8; \
298 static void fx_ldw_r0() { FX_LDW(0); }
299 static void fx_ldw_r1() { FX_LDW(1); }
300 static void fx_ldw_r2() { FX_LDW(2); }
301 static void fx_ldw_r3() { FX_LDW(3); }
302 static void fx_ldw_r4() { FX_LDW(4); }
303 static void fx_ldw_r5() { FX_LDW(5); }
304 static void fx_ldw_r6() { FX_LDW(6); }
305 static void fx_ldw_r7() { FX_LDW(7); }
306 static void fx_ldw_r8() { FX_LDW(8); }
307 static void fx_ldw_r9() { FX_LDW(9); }
308 static void fx_ldw_r10() { FX_LDW(10); }
309 static void fx_ldw_r11() { FX_LDW(11); }
311 /* 40-4b(ALT1) - ldb (rn) - load byte */
312 #define FX_LDB(reg) uint32 v; \
313 GSU.vLastRamAdr = GSU.avReg[reg]; \
314 v = (uint32)RAM(GSU.avReg[reg]); \
318 static void fx_ldb_r0() { FX_LDB(0); }
319 static void fx_ldb_r1() { FX_LDB(1); }
320 static void fx_ldb_r2() { FX_LDB(2); }
321 static void fx_ldb_r3() { FX_LDB(3); }
322 static void fx_ldb_r4() { FX_LDB(4); }
323 static void fx_ldb_r5() { FX_LDB(5); }
324 static void fx_ldb_r6() { FX_LDB(6); }
325 static void fx_ldb_r7() { FX_LDB(7); }
326 static void fx_ldb_r8() { FX_LDB(8); }
327 static void fx_ldb_r9() { FX_LDB(9); }
328 static void fx_ldb_r10() { FX_LDB(10); }
329 static void fx_ldb_r11() { FX_LDB(11); }
331 /* 4c - plot - plot pixel with R1,R2 as x,y and the color register as the color */
332 static void fx_plot_2bit()
334 uint32 x = USEX8(R1);
335 uint32 y = USEX8(R2);
344 if(y >= GSU.vScreenHeight) return;
346 if(GSU.vPlotOptionReg & 0x02)
347 c = (x^y)&1 ? (uint8)(GSU.vColorReg>>4) : (uint8)GSU.vColorReg;
349 c = (uint8)GSU.vColorReg;
351 if( !(GSU.vPlotOptionReg & 0x01) && !(c & 0xf)) return;
352 a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1);
355 if(c & 0x01) a[0] |= v;
357 if(c & 0x02) a[1] |= v;
361 /* 2c(ALT1) - rpix - read color of the pixel with R1,R2 as x,y */
362 static void fx_rpix_2bit()
364 uint32 x = USEX8(R1);
365 uint32 y = USEX8(R2);
372 if(y >= GSU.vScreenHeight) return;
375 a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1);
379 DREG |= ((uint32)((a[0] & v) != 0)) << 0;
380 DREG |= ((uint32)((a[1] & v) != 0)) << 1;
384 /* 4c - plot - plot pixel with R1,R2 as x,y and the color register as the color */
385 static void fx_plot_4bit()
387 uint32 x = USEX8(R1);
388 uint32 y = USEX8(R2);
397 if(y >= GSU.vScreenHeight) return;
399 if(GSU.vPlotOptionReg & 0x02)
400 c = (x^y)&1 ? (uint8)(GSU.vColorReg>>4) : (uint8)GSU.vColorReg;
402 c = (uint8)GSU.vColorReg;
404 if( !(GSU.vPlotOptionReg & 0x01) && !(c & 0xf)) return;
406 a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1);
409 if(c & 0x01) a[0x00] |= v;
411 if(c & 0x02) a[0x01] |= v;
413 if(c & 0x04) a[0x10] |= v;
415 if(c & 0x08) a[0x11] |= v;
419 /* 4c(ALT1) - rpix - read color of the pixel with R1,R2 as x,y */
420 static void fx_rpix_4bit()
422 uint32 x = USEX8(R1);
423 uint32 y = USEX8(R2);
431 if(y >= GSU.vScreenHeight) return;
434 a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1);
438 DREG |= ((uint32)((a[0x00] & v) != 0)) << 0;
439 DREG |= ((uint32)((a[0x01] & v) != 0)) << 1;
440 DREG |= ((uint32)((a[0x10] & v) != 0)) << 2;
441 DREG |= ((uint32)((a[0x11] & v) != 0)) << 3;
445 /* 8c - plot - plot pixel with R1,R2 as x,y and the color register as the color */
446 static void fx_plot_8bit()
448 uint32 x = USEX8(R1);
449 uint32 y = USEX8(R2);
458 if(y >= GSU.vScreenHeight) return;
460 c = (uint8)GSU.vColorReg;
461 if(GSU.vPlotOptionReg & 0x10) {
462 if( !(GSU.vPlotOptionReg & 0x01) && !(c&0xf)) return;
464 if( !(GSU.vPlotOptionReg & 0x01) && !c) return;
467 a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1);
470 if(c & 0x01) a[0x00] |= v;
472 if(c & 0x02) a[0x01] |= v;
474 if(c & 0x04) a[0x10] |= v;
476 if(c & 0x08) a[0x11] |= v;
478 if(c & 0x10) a[0x20] |= v;
480 if(c & 0x20) a[0x21] |= v;
482 if(c & 0x40) a[0x30] |= v;
484 if(c & 0x80) a[0x31] |= v;
488 /* 4c(ALT1) - rpix - read color of the pixel with R1,R2 as x,y */
489 static void fx_rpix_8bit()
491 uint32 x = USEX8(R1);
492 uint32 y = USEX8(R2);
500 if(y >= GSU.vScreenHeight) return;
502 a = GSU.apvScreen[y >> 3] + GSU.x[x >> 3] + ((y & 7) << 1);
506 DREG |= ((uint32)((a[0x00] & v) != 0)) << 0;
507 DREG |= ((uint32)((a[0x01] & v) != 0)) << 1;
508 DREG |= ((uint32)((a[0x10] & v) != 0)) << 2;
509 DREG |= ((uint32)((a[0x11] & v) != 0)) << 3;
510 DREG |= ((uint32)((a[0x20] & v) != 0)) << 4;
511 DREG |= ((uint32)((a[0x21] & v) != 0)) << 5;
512 DREG |= ((uint32)((a[0x30] & v) != 0)) << 6;
513 DREG |= ((uint32)((a[0x31] & v) != 0)) << 7;
517 /* 4o - plot - plot pixel with R1,R2 as x,y and the color register as the color */
518 static void fx_plot_obj()
520 printf ("ERROR fx_plot_obj called\n");
523 /* 4c(ALT1) - rpix - read color of the pixel with R1,R2 as x,y */
524 static void fx_rpix_obj()
526 printf ("ERROR fx_rpix_obj called\n");
529 /* 4d - swap - swap upper and lower byte of a register */
530 static void fx_swap()
532 uint8 c = (uint8)SREG;
533 uint8 d = (uint8)(SREG>>8);
534 uint32 v = (((uint32)c)<<8)|((uint32)d);
542 /* 4e - color - copy source register to color register */
543 static void fx_color()
545 uint8 c = (uint8)SREG;
546 if(GSU.vPlotOptionReg & 0x04)
547 c = (c&0xf0) | (c>>4);
548 if(GSU.vPlotOptionReg & 0x08)
550 GSU.vColorReg &= 0xf0;
551 GSU.vColorReg |= c & 0x0f;
554 GSU.vColorReg = USEX8(c);
559 /* 4e(ALT1) - cmode - set plot option register */
560 static void fx_cmode()
562 GSU.vPlotOptionReg = SREG;
564 if(GSU.vPlotOptionReg & 0x10)
566 /* OBJ Mode (for drawing into sprites) */
567 GSU.vScreenHeight = 256;
570 GSU.vScreenHeight = GSU.vScreenRealHeight;
572 fx_computeScreenPointers ();
577 /* 4f - not - perform exclusive exor with 1 on all bits */
588 /* 50-5f - add rn - add, register + register */
589 #define FX_ADD(reg) \
590 int32 s = SUSEX16(SREG) + SUSEX16(GSU.avReg[reg]); \
591 GSU.vCarry = s >= 0x10000; \
592 GSU.vOverflow = ~(SREG ^ GSU.avReg[reg]) & (GSU.avReg[reg] ^ s) & 0x8000; \
598 static void fx_add_r0() { FX_ADD(0); }
599 static void fx_add_r1() { FX_ADD(1); }
600 static void fx_add_r2() { FX_ADD(2); }
601 static void fx_add_r3() { FX_ADD(3); }
602 static void fx_add_r4() { FX_ADD(4); }
603 static void fx_add_r5() { FX_ADD(5); }
604 static void fx_add_r6() { FX_ADD(6); }
605 static void fx_add_r7() { FX_ADD(7); }
606 static void fx_add_r8() { FX_ADD(8); }
607 static void fx_add_r9() { FX_ADD(9); }
608 static void fx_add_r10() { FX_ADD(10); }
609 static void fx_add_r11() { FX_ADD(11); }
610 static void fx_add_r12() { FX_ADD(12); }
611 static void fx_add_r13() { FX_ADD(13); }
612 static void fx_add_r14() { FX_ADD(14); }
613 static void fx_add_r15() { FX_ADD(15); }
615 /* 50-5f(ALT1) - adc rn - add with carry, register + register */
616 #define FX_ADC(reg) \
617 int32 s = SUSEX16(SREG) + SUSEX16(GSU.avReg[reg]) + SEX16(GSU.vCarry); \
618 GSU.vCarry = s >= 0x10000; \
619 GSU.vOverflow = ~(SREG ^ GSU.avReg[reg]) & (GSU.avReg[reg] ^ s) & 0x8000; \
625 static void fx_adc_r0() { FX_ADC(0); }
626 static void fx_adc_r1() { FX_ADC(1); }
627 static void fx_adc_r2() { FX_ADC(2); }
628 static void fx_adc_r3() { FX_ADC(3); }
629 static void fx_adc_r4() { FX_ADC(4); }
630 static void fx_adc_r5() { FX_ADC(5); }
631 static void fx_adc_r6() { FX_ADC(6); }
632 static void fx_adc_r7() { FX_ADC(7); }
633 static void fx_adc_r8() { FX_ADC(8); }
634 static void fx_adc_r9() { FX_ADC(9); }
635 static void fx_adc_r10() { FX_ADC(10); }
636 static void fx_adc_r11() { FX_ADC(11); }
637 static void fx_adc_r12() { FX_ADC(12); }
638 static void fx_adc_r13() { FX_ADC(13); }
639 static void fx_adc_r14() { FX_ADC(14); }
640 static void fx_adc_r15() { FX_ADC(15); }
642 /* 50-5f(ALT2) - add #n - add, register + immediate */
643 #define FX_ADD_I(imm) \
644 int32 s = SUSEX16(SREG) + imm; \
645 GSU.vCarry = s >= 0x10000; \
646 GSU.vOverflow = ~(SREG ^ imm) & (imm ^ s) & 0x8000; \
652 static void fx_add_i0() { FX_ADD_I(0); }
653 static void fx_add_i1() { FX_ADD_I(1); }
654 static void fx_add_i2() { FX_ADD_I(2); }
655 static void fx_add_i3() { FX_ADD_I(3); }
656 static void fx_add_i4() { FX_ADD_I(4); }
657 static void fx_add_i5() { FX_ADD_I(5); }
658 static void fx_add_i6() { FX_ADD_I(6); }
659 static void fx_add_i7() { FX_ADD_I(7); }
660 static void fx_add_i8() { FX_ADD_I(8); }
661 static void fx_add_i9() { FX_ADD_I(9); }
662 static void fx_add_i10() { FX_ADD_I(10); }
663 static void fx_add_i11() { FX_ADD_I(11); }
664 static void fx_add_i12() { FX_ADD_I(12); }
665 static void fx_add_i13() { FX_ADD_I(13); }
666 static void fx_add_i14() { FX_ADD_I(14); }
667 static void fx_add_i15() { FX_ADD_I(15); }
669 /* 50-5f(ALT3) - adc #n - add with carry, register + immediate */
670 #define FX_ADC_I(imm) \
671 int32 s = SUSEX16(SREG) + imm + SUSEX16(GSU.vCarry); \
672 GSU.vCarry = s >= 0x10000; \
673 GSU.vOverflow = ~(SREG ^ imm) & (imm ^ s) & 0x8000; \
679 static void fx_adc_i0() { FX_ADC_I(0); }
680 static void fx_adc_i1() { FX_ADC_I(1); }
681 static void fx_adc_i2() { FX_ADC_I(2); }
682 static void fx_adc_i3() { FX_ADC_I(3); }
683 static void fx_adc_i4() { FX_ADC_I(4); }
684 static void fx_adc_i5() { FX_ADC_I(5); }
685 static void fx_adc_i6() { FX_ADC_I(6); }
686 static void fx_adc_i7() { FX_ADC_I(7); }
687 static void fx_adc_i8() { FX_ADC_I(8); }
688 static void fx_adc_i9() { FX_ADC_I(9); }
689 static void fx_adc_i10() { FX_ADC_I(10); }
690 static void fx_adc_i11() { FX_ADC_I(11); }
691 static void fx_adc_i12() { FX_ADC_I(12); }
692 static void fx_adc_i13() { FX_ADC_I(13); }
693 static void fx_adc_i14() { FX_ADC_I(14); }
694 static void fx_adc_i15() { FX_ADC_I(15); }
696 /* 60-6f - sub rn - subtract, register - register */
697 #define FX_SUB(reg) \
698 int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]); \
699 GSU.vCarry = s >= 0; \
700 GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \
706 static void fx_sub_r0() { FX_SUB(0); }
707 static void fx_sub_r1() { FX_SUB(1); }
708 static void fx_sub_r2() { FX_SUB(2); }
709 static void fx_sub_r3() { FX_SUB(3); }
710 static void fx_sub_r4() { FX_SUB(4); }
711 static void fx_sub_r5() { FX_SUB(5); }
712 static void fx_sub_r6() { FX_SUB(6); }
713 static void fx_sub_r7() { FX_SUB(7); }
714 static void fx_sub_r8() { FX_SUB(8); }
715 static void fx_sub_r9() { FX_SUB(9); }
716 static void fx_sub_r10() { FX_SUB(10); }
717 static void fx_sub_r11() { FX_SUB(11); }
718 static void fx_sub_r12() { FX_SUB(12); }
719 static void fx_sub_r13() { FX_SUB(13); }
720 static void fx_sub_r14() { FX_SUB(14); }
721 static void fx_sub_r15() { FX_SUB(15); }
723 /* 60-6f(ALT1) - sbc rn - subtract with carry, register - register */
724 #define FX_SBC(reg) \
725 int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]) - (SUSEX16(GSU.vCarry^1)); \
726 GSU.vCarry = s >= 0; \
727 GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \
733 static void fx_sbc_r0() { FX_SBC(0); }
734 static void fx_sbc_r1() { FX_SBC(1); }
735 static void fx_sbc_r2() { FX_SBC(2); }
736 static void fx_sbc_r3() { FX_SBC(3); }
737 static void fx_sbc_r4() { FX_SBC(4); }
738 static void fx_sbc_r5() { FX_SBC(5); }
739 static void fx_sbc_r6() { FX_SBC(6); }
740 static void fx_sbc_r7() { FX_SBC(7); }
741 static void fx_sbc_r8() { FX_SBC(8); }
742 static void fx_sbc_r9() { FX_SBC(9); }
743 static void fx_sbc_r10() { FX_SBC(10); }
744 static void fx_sbc_r11() { FX_SBC(11); }
745 static void fx_sbc_r12() { FX_SBC(12); }
746 static void fx_sbc_r13() { FX_SBC(13); }
747 static void fx_sbc_r14() { FX_SBC(14); }
748 static void fx_sbc_r15() { FX_SBC(15); }
750 /* 60-6f(ALT2) - sub #n - subtract, register - immediate */
751 #define FX_SUB_I(imm) \
752 int32 s = SUSEX16(SREG) - imm; \
753 GSU.vCarry = s >= 0; \
754 GSU.vOverflow = (SREG ^ imm) & (SREG ^ s) & 0x8000; \
760 static void fx_sub_i0() { FX_SUB_I(0); }
761 static void fx_sub_i1() { FX_SUB_I(1); }
762 static void fx_sub_i2() { FX_SUB_I(2); }
763 static void fx_sub_i3() { FX_SUB_I(3); }
764 static void fx_sub_i4() { FX_SUB_I(4); }
765 static void fx_sub_i5() { FX_SUB_I(5); }
766 static void fx_sub_i6() { FX_SUB_I(6); }
767 static void fx_sub_i7() { FX_SUB_I(7); }
768 static void fx_sub_i8() { FX_SUB_I(8); }
769 static void fx_sub_i9() { FX_SUB_I(9); }
770 static void fx_sub_i10() { FX_SUB_I(10); }
771 static void fx_sub_i11() { FX_SUB_I(11); }
772 static void fx_sub_i12() { FX_SUB_I(12); }
773 static void fx_sub_i13() { FX_SUB_I(13); }
774 static void fx_sub_i14() { FX_SUB_I(14); }
775 static void fx_sub_i15() { FX_SUB_I(15); }
777 /* 60-6f(ALT3) - cmp rn - compare, register, register */
778 #define FX_CMP(reg) \
779 int32 s = SUSEX16(SREG) - SUSEX16(GSU.avReg[reg]); \
780 GSU.vCarry = s >= 0; \
781 GSU.vOverflow = (SREG ^ GSU.avReg[reg]) & (SREG ^ s) & 0x8000; \
786 static void fx_cmp_r0() { FX_CMP(0); }
787 static void fx_cmp_r1() { FX_CMP(1); }
788 static void fx_cmp_r2() { FX_CMP(2); }
789 static void fx_cmp_r3() { FX_CMP(3); }
790 static void fx_cmp_r4() { FX_CMP(4); }
791 static void fx_cmp_r5() { FX_CMP(5); }
792 static void fx_cmp_r6() { FX_CMP(6); }
793 static void fx_cmp_r7() { FX_CMP(7); }
794 static void fx_cmp_r8() { FX_CMP(8); }
795 static void fx_cmp_r9() { FX_CMP(9); }
796 static void fx_cmp_r10() { FX_CMP(10); }
797 static void fx_cmp_r11() { FX_CMP(11); }
798 static void fx_cmp_r12() { FX_CMP(12); }
799 static void fx_cmp_r13() { FX_CMP(13); }
800 static void fx_cmp_r14() { FX_CMP(14); }
801 static void fx_cmp_r15() { FX_CMP(15); }
803 /* 70 - merge - R7 as upper byte, R8 as lower byte (used for texture-mapping) */
804 static void fx_merge()
806 uint32 v = (R7&0xff00) | ((R8&0xff00)>>8);
808 GSU.vOverflow = (v & 0xc0c0) << 16;
809 GSU.vZero = !(v & 0xf0f0);
810 GSU.vSign = ((v | (v<<8)) & 0x8000);
811 GSU.vCarry = (v & 0xe0e0) != 0;
816 /* 71-7f - and rn - reister & register */
817 #define FX_AND(reg) \
818 uint32 v = SREG & GSU.avReg[reg]; \
824 static void fx_and_r1() { FX_AND(1); }
825 static void fx_and_r2() { FX_AND(2); }
826 static void fx_and_r3() { FX_AND(3); }
827 static void fx_and_r4() { FX_AND(4); }
828 static void fx_and_r5() { FX_AND(5); }
829 static void fx_and_r6() { FX_AND(6); }
830 static void fx_and_r7() { FX_AND(7); }
831 static void fx_and_r8() { FX_AND(8); }
832 static void fx_and_r9() { FX_AND(9); }
833 static void fx_and_r10() { FX_AND(10); }
834 static void fx_and_r11() { FX_AND(11); }
835 static void fx_and_r12() { FX_AND(12); }
836 static void fx_and_r13() { FX_AND(13); }
837 static void fx_and_r14() { FX_AND(14); }
838 static void fx_and_r15() { FX_AND(15); }
840 /* 71-7f(ALT1) - bic rn - reister & ~register */
841 #define FX_BIC(reg) \
842 uint32 v = SREG & ~GSU.avReg[reg]; \
848 static void fx_bic_r1() { FX_AND(1); }
849 static void fx_bic_r2() { FX_AND(2); }
850 static void fx_bic_r3() { FX_AND(3); }
851 static void fx_bic_r4() { FX_AND(4); }
852 static void fx_bic_r5() { FX_AND(5); }
853 static void fx_bic_r6() { FX_AND(6); }
854 static void fx_bic_r7() { FX_AND(7); }
855 static void fx_bic_r8() { FX_AND(8); }
856 static void fx_bic_r9() { FX_AND(9); }
857 static void fx_bic_r10() { FX_AND(10); }
858 static void fx_bic_r11() { FX_AND(11); }
859 static void fx_bic_r12() { FX_AND(12); }
860 static void fx_bic_r13() { FX_AND(13); }
861 static void fx_bic_r14() { FX_AND(14); }
862 static void fx_bic_r15() { FX_AND(15); }
864 /* 71-7f(ALT2) - and #n - reister & immediate */
865 #define FX_AND_I(imm) \
866 uint32 v = SREG & imm; \
872 static void fx_and_i1() { FX_AND_I(1); }
873 static void fx_and_i2() { FX_AND_I(2); }
874 static void fx_and_i3() { FX_AND_I(3); }
875 static void fx_and_i4() { FX_AND_I(4); }
876 static void fx_and_i5() { FX_AND_I(5); }
877 static void fx_and_i6() { FX_AND_I(6); }
878 static void fx_and_i7() { FX_AND_I(7); }
879 static void fx_and_i8() { FX_AND_I(8); }
880 static void fx_and_i9() { FX_AND_I(9); }
881 static void fx_and_i10() { FX_AND_I(10); }
882 static void fx_and_i11() { FX_AND_I(11); }
883 static void fx_and_i12() { FX_AND_I(12); }
884 static void fx_and_i13() { FX_AND_I(13); }
885 static void fx_and_i14() { FX_AND_I(14); }
886 static void fx_and_i15() { FX_AND_I(15); }
888 /* 71-7f(ALT3) - bic #n - reister & ~immediate */
889 #define FX_BIC_I(imm) \
890 uint32 v = SREG & ~imm; \
896 static void fx_bic_i1() { FX_BIC_I(1); }
897 static void fx_bic_i2() { FX_BIC_I(2); }
898 static void fx_bic_i3() { FX_BIC_I(3); }
899 static void fx_bic_i4() { FX_BIC_I(4); }
900 static void fx_bic_i5() { FX_BIC_I(5); }
901 static void fx_bic_i6() { FX_BIC_I(6); }
902 static void fx_bic_i7() { FX_BIC_I(7); }
903 static void fx_bic_i8() { FX_BIC_I(8); }
904 static void fx_bic_i9() { FX_BIC_I(9); }
905 static void fx_bic_i10() { FX_BIC_I(10); }
906 static void fx_bic_i11() { FX_BIC_I(11); }
907 static void fx_bic_i12() { FX_BIC_I(12); }
908 static void fx_bic_i13() { FX_BIC_I(13); }
909 static void fx_bic_i14() { FX_BIC_I(14); }
910 static void fx_bic_i15() { FX_BIC_I(15); }
912 /* 80-8f - mult rn - 8 bit to 16 bit signed multiply, register * register */
913 #define FX_MULT(reg) \
914 uint32 v = (uint32)(SEX8(SREG) * SEX8(GSU.avReg[reg])); \
920 static void fx_mult_r0() { FX_MULT(0); }
921 static void fx_mult_r1() { FX_MULT(1); }
922 static void fx_mult_r2() { FX_MULT(2); }
923 static void fx_mult_r3() { FX_MULT(3); }
924 static void fx_mult_r4() { FX_MULT(4); }
925 static void fx_mult_r5() { FX_MULT(5); }
926 static void fx_mult_r6() { FX_MULT(6); }
927 static void fx_mult_r7() { FX_MULT(7); }
928 static void fx_mult_r8() { FX_MULT(8); }
929 static void fx_mult_r9() { FX_MULT(9); }
930 static void fx_mult_r10() { FX_MULT(10); }
931 static void fx_mult_r11() { FX_MULT(11); }
932 static void fx_mult_r12() { FX_MULT(12); }
933 static void fx_mult_r13() { FX_MULT(13); }
934 static void fx_mult_r14() { FX_MULT(14); }
935 static void fx_mult_r15() { FX_MULT(15); }
937 /* 80-8f(ALT1) - umult rn - 8 bit to 16 bit unsigned multiply, register * register */
938 #define FX_UMULT(reg) \
939 uint32 v = USEX8(SREG) * USEX8(GSU.avReg[reg]); \
945 static void fx_umult_r0() { FX_UMULT(0); }
946 static void fx_umult_r1() { FX_UMULT(1); }
947 static void fx_umult_r2() { FX_UMULT(2); }
948 static void fx_umult_r3() { FX_UMULT(3); }
949 static void fx_umult_r4() { FX_UMULT(4); }
950 static void fx_umult_r5() { FX_UMULT(5); }
951 static void fx_umult_r6() { FX_UMULT(6); }
952 static void fx_umult_r7() { FX_UMULT(7); }
953 static void fx_umult_r8() { FX_UMULT(8); }
954 static void fx_umult_r9() { FX_UMULT(9); }
955 static void fx_umult_r10() { FX_UMULT(10); }
956 static void fx_umult_r11() { FX_UMULT(11); }
957 static void fx_umult_r12() { FX_UMULT(12); }
958 static void fx_umult_r13() { FX_UMULT(13); }
959 static void fx_umult_r14() { FX_UMULT(14); }
960 static void fx_umult_r15() { FX_UMULT(15); }
962 /* 80-8f(ALT2) - mult #n - 8 bit to 16 bit signed multiply, register * immediate */
963 #define FX_MULT_I(imm) \
964 uint32 v = (uint32) (SEX8(SREG) * ((int32)imm)); \
970 static void fx_mult_i0() { FX_MULT_I(0); }
971 static void fx_mult_i1() { FX_MULT_I(1); }
972 static void fx_mult_i2() { FX_MULT_I(2); }
973 static void fx_mult_i3() { FX_MULT_I(3); }
974 static void fx_mult_i4() { FX_MULT_I(4); }
975 static void fx_mult_i5() { FX_MULT_I(5); }
976 static void fx_mult_i6() { FX_MULT_I(6); }
977 static void fx_mult_i7() { FX_MULT_I(7); }
978 static void fx_mult_i8() { FX_MULT_I(8); }
979 static void fx_mult_i9() { FX_MULT_I(9); }
980 static void fx_mult_i10() { FX_MULT_I(10); }
981 static void fx_mult_i11() { FX_MULT_I(11); }
982 static void fx_mult_i12() { FX_MULT_I(12); }
983 static void fx_mult_i13() { FX_MULT_I(13); }
984 static void fx_mult_i14() { FX_MULT_I(14); }
985 static void fx_mult_i15() { FX_MULT_I(15); }
987 /* 80-8f(ALT3) - umult #n - 8 bit to 16 bit unsigned multiply, register * immediate */
988 #define FX_UMULT_I(imm) \
989 uint32 v = USEX8(SREG) * ((uint32)imm); \
995 static void fx_umult_i0() { FX_UMULT_I(0); }
996 static void fx_umult_i1() { FX_UMULT_I(1); }
997 static void fx_umult_i2() { FX_UMULT_I(2); }
998 static void fx_umult_i3() { FX_UMULT_I(3); }
999 static void fx_umult_i4() { FX_UMULT_I(4); }
1000 static void fx_umult_i5() { FX_UMULT_I(5); }
1001 static void fx_umult_i6() { FX_UMULT_I(6); }
1002 static void fx_umult_i7() { FX_UMULT_I(7); }
1003 static void fx_umult_i8() { FX_UMULT_I(8); }
1004 static void fx_umult_i9() { FX_UMULT_I(9); }
1005 static void fx_umult_i10() { FX_UMULT_I(10); }
1006 static void fx_umult_i11() { FX_UMULT_I(11); }
1007 static void fx_umult_i12() { FX_UMULT_I(12); }
1008 static void fx_umult_i13() { FX_UMULT_I(13); }
1009 static void fx_umult_i14() { FX_UMULT_I(14); }
1010 static void fx_umult_i15() { FX_UMULT_I(15); }
1012 /* 90 - sbk - store word to last accessed RAM address */
1013 static void fx_sbk()
1015 RAM(GSU.vLastRamAdr) = (uint8)SREG;
1016 RAM(GSU.vLastRamAdr^1) = (uint8)(SREG>>8);
1021 /* 91-94 - link #n - R11 = R15 + immediate */
1022 #define FX_LINK_I(lkn) R11 = R15 + lkn; CLRFLAGS; R15++
1023 static void fx_link_i1() { FX_LINK_I(1); }
1024 static void fx_link_i2() { FX_LINK_I(2); }
1025 static void fx_link_i3() { FX_LINK_I(3); }
1026 static void fx_link_i4() { FX_LINK_I(4); }
1028 /* 95 - sex - sign extend 8 bit to 16 bit */
1029 static void fx_sex()
1031 uint32 v = (uint32)SEX8(SREG);
1039 /* 96 - asr - aritmetric shift right by one */
1040 static void fx_asr()
1043 GSU.vCarry = SREG & 1;
1044 v = (uint32)(SEX16(SREG)>>1);
1052 /* 96(ALT1) - div2 - aritmetric shift right by one */
1053 static void fx_div2()
1056 int32 s = SEX16(SREG);
1069 /* 97 - ror - rotate right by one */
1070 static void fx_ror()
1072 uint32 v = (USEX16(SREG)>>1) | (GSU.vCarry<<15);
1073 GSU.vCarry = SREG & 1;
1081 /* 98-9d - jmp rn - jump to address of register */
1082 #define FX_JMP(reg) \
1083 R15 = GSU.avReg[reg]; \
1085 static void fx_jmp_r8() { FX_JMP(8); }
1086 static void fx_jmp_r9() { FX_JMP(9); }
1087 static void fx_jmp_r10() { FX_JMP(10); }
1088 static void fx_jmp_r11() { FX_JMP(11); }
1089 static void fx_jmp_r12() { FX_JMP(12); }
1090 static void fx_jmp_r13() { FX_JMP(13); }
1092 /* 98-9d(ALT1) - ljmp rn - set program bank to source register and jump to address of register */
1093 #define FX_LJMP(reg) \
1094 GSU.vPrgBankReg = GSU.avReg[reg] & 0x7f; \
1095 GSU.pvPrgBank = GSU.apvRomBank[GSU.vPrgBankReg]; \
1097 GSU.bCacheActive = FALSE; fx_cache(); R15--;
1098 static void fx_ljmp_r8() { FX_LJMP(8); }
1099 static void fx_ljmp_r9() { FX_LJMP(9); }
1100 static void fx_ljmp_r10() { FX_LJMP(10); }
1101 static void fx_ljmp_r11() { FX_LJMP(11); }
1102 static void fx_ljmp_r12() { FX_LJMP(12); }
1103 static void fx_ljmp_r13() { FX_LJMP(13); }
1105 /* 9e - lob - set upper byte to zero (keep low byte) */
1106 static void fx_lob()
1108 uint32 v = USEX8(SREG);
1116 /* 9f - fmult - 16 bit to 32 bit signed multiplication, upper 16 bits only */
1117 static void fx_fmult()
1120 uint32 c = (uint32) (SEX16(SREG) * SEX16(R6));
1125 GSU.vCarry = (c >> 15) & 1;
1130 /* 9f(ALT1) - lmult - 16 bit to 32 bit signed multiplication */
1131 static void fx_lmult()
1134 uint32 c = (uint32) (SEX16(SREG) * SEX16(R6));
1141 GSU.vCarry = (R4 >> 15) & 1; /* should it be bit 15 of R4 instead? */
1146 /* a0-af - ibt rn,#pp - immediate byte transfer */
1147 #define FX_IBT(reg) \
1148 uint8 v = PIPE; R15++; \
1150 GSU.avReg[reg] = SEX8(v); \
1152 static void fx_ibt_r0() { FX_IBT(0); }
1153 static void fx_ibt_r1() { FX_IBT(1); }
1154 static void fx_ibt_r2() { FX_IBT(2); }
1155 static void fx_ibt_r3() { FX_IBT(3); }
1156 static void fx_ibt_r4() { FX_IBT(4); }
1157 static void fx_ibt_r5() { FX_IBT(5); }
1158 static void fx_ibt_r6() { FX_IBT(6); }
1159 static void fx_ibt_r7() { FX_IBT(7); }
1160 static void fx_ibt_r8() { FX_IBT(8); }
1161 static void fx_ibt_r9() { FX_IBT(9); }
1162 static void fx_ibt_r10() { FX_IBT(10); }
1163 static void fx_ibt_r11() { FX_IBT(11); }
1164 static void fx_ibt_r12() { FX_IBT(12); }
1165 static void fx_ibt_r13() { FX_IBT(13); }
1166 static void fx_ibt_r14() { FX_IBT(14); READR14; }
1167 static void fx_ibt_r15() { FX_IBT(15); }
1169 /* a0-af(ALT1) - lms rn,(yy) - load word from RAM (short address) */
1170 #define FX_LMS(reg) \
1171 GSU.vLastRamAdr = ((uint32)PIPE) << 1; \
1172 R15++; FETCHPIPE; R15++; \
1173 GSU.avReg[reg] = (uint32)RAM(GSU.vLastRamAdr); \
1174 GSU.avReg[reg] |= ((uint32)RAM(GSU.vLastRamAdr+1))<<8; \
1176 static void fx_lms_r0() { FX_LMS(0); }
1177 static void fx_lms_r1() { FX_LMS(1); }
1178 static void fx_lms_r2() { FX_LMS(2); }
1179 static void fx_lms_r3() { FX_LMS(3); }
1180 static void fx_lms_r4() { FX_LMS(4); }
1181 static void fx_lms_r5() { FX_LMS(5); }
1182 static void fx_lms_r6() { FX_LMS(6); }
1183 static void fx_lms_r7() { FX_LMS(7); }
1184 static void fx_lms_r8() { FX_LMS(8); }
1185 static void fx_lms_r9() { FX_LMS(9); }
1186 static void fx_lms_r10() { FX_LMS(10); }
1187 static void fx_lms_r11() { FX_LMS(11); }
1188 static void fx_lms_r12() { FX_LMS(12); }
1189 static void fx_lms_r13() { FX_LMS(13); }
1190 static void fx_lms_r14() { FX_LMS(14); READR14; }
1191 static void fx_lms_r15() { FX_LMS(15); }
1193 /* a0-af(ALT2) - sms (yy),rn - store word in RAM (short address) */
1194 /* If rn == r15, is the value of r15 before or after the extra byte is read? */
1195 #define FX_SMS(reg) \
1196 uint32 v = GSU.avReg[reg]; \
1197 GSU.vLastRamAdr = ((uint32)PIPE) << 1; \
1199 RAM(GSU.vLastRamAdr) = (uint8)v; \
1200 RAM(GSU.vLastRamAdr+1) = (uint8)(v>>8); \
1202 static void fx_sms_r0() { FX_SMS(0); }
1203 static void fx_sms_r1() { FX_SMS(1); }
1204 static void fx_sms_r2() { FX_SMS(2); }
1205 static void fx_sms_r3() { FX_SMS(3); }
1206 static void fx_sms_r4() { FX_SMS(4); }
1207 static void fx_sms_r5() { FX_SMS(5); }
1208 static void fx_sms_r6() { FX_SMS(6); }
1209 static void fx_sms_r7() { FX_SMS(7); }
1210 static void fx_sms_r8() { FX_SMS(8); }
1211 static void fx_sms_r9() { FX_SMS(9); }
1212 static void fx_sms_r10() { FX_SMS(10); }
1213 static void fx_sms_r11() { FX_SMS(11); }
1214 static void fx_sms_r12() { FX_SMS(12); }
1215 static void fx_sms_r13() { FX_SMS(13); }
1216 static void fx_sms_r14() { FX_SMS(14); }
1217 static void fx_sms_r15() { FX_SMS(15); }
1219 /* b0-bf - from rn - set source register */
1220 /* b0-bf(B) - moves rn - move register to register, and set flags, (if B flag is set) */
1221 #define FX_FROM(reg) \
1222 if(TF(B)) { uint32 v = GSU.avReg[reg]; R15++; DREG = v; \
1223 GSU.vOverflow = (v&0x80) << 16; GSU.vSign = v; GSU.vZero = v; TESTR14; CLRFLAGS; } \
1224 else { GSU.pvSreg = &GSU.avReg[reg]; R15++; }
1225 static void fx_from_r0() { FX_FROM(0); }
1226 static void fx_from_r1() { FX_FROM(1); }
1227 static void fx_from_r2() { FX_FROM(2); }
1228 static void fx_from_r3() { FX_FROM(3); }
1229 static void fx_from_r4() { FX_FROM(4); }
1230 static void fx_from_r5() { FX_FROM(5); }
1231 static void fx_from_r6() { FX_FROM(6); }
1232 static void fx_from_r7() { FX_FROM(7); }
1233 static void fx_from_r8() { FX_FROM(8); }
1234 static void fx_from_r9() { FX_FROM(9); }
1235 static void fx_from_r10() { FX_FROM(10); }
1236 static void fx_from_r11() { FX_FROM(11); }
1237 static void fx_from_r12() { FX_FROM(12); }
1238 static void fx_from_r13() { FX_FROM(13); }
1239 static void fx_from_r14() { FX_FROM(14); }
1240 static void fx_from_r15() { FX_FROM(15); }
1242 /* c0 - hib - move high-byte to low-byte */
1243 static void fx_hib()
1245 uint32 v = USEX8(SREG>>8);
1254 #define FX_OR(reg) \
1255 uint32 v = SREG | GSU.avReg[reg]; R15++; DREG = v; \
1260 static void fx_or_r1() { FX_OR(1); }
1261 static void fx_or_r2() { FX_OR(2); }
1262 static void fx_or_r3() { FX_OR(3); }
1263 static void fx_or_r4() { FX_OR(4); }
1264 static void fx_or_r5() { FX_OR(5); }
1265 static void fx_or_r6() { FX_OR(6); }
1266 static void fx_or_r7() { FX_OR(7); }
1267 static void fx_or_r8() { FX_OR(8); }
1268 static void fx_or_r9() { FX_OR(9); }
1269 static void fx_or_r10() { FX_OR(10); }
1270 static void fx_or_r11() { FX_OR(11); }
1271 static void fx_or_r12() { FX_OR(12); }
1272 static void fx_or_r13() { FX_OR(13); }
1273 static void fx_or_r14() { FX_OR(14); }
1274 static void fx_or_r15() { FX_OR(15); }
1276 /* c1-cf(ALT1) - xor rn */
1277 #define FX_XOR(reg) \
1278 uint32 v = SREG ^ GSU.avReg[reg]; R15++; DREG = v; \
1283 static void fx_xor_r1() { FX_XOR(1); }
1284 static void fx_xor_r2() { FX_XOR(2); }
1285 static void fx_xor_r3() { FX_XOR(3); }
1286 static void fx_xor_r4() { FX_XOR(4); }
1287 static void fx_xor_r5() { FX_XOR(5); }
1288 static void fx_xor_r6() { FX_XOR(6); }
1289 static void fx_xor_r7() { FX_XOR(7); }
1290 static void fx_xor_r8() { FX_XOR(8); }
1291 static void fx_xor_r9() { FX_XOR(9); }
1292 static void fx_xor_r10() { FX_XOR(10); }
1293 static void fx_xor_r11() { FX_XOR(11); }
1294 static void fx_xor_r12() { FX_XOR(12); }
1295 static void fx_xor_r13() { FX_XOR(13); }
1296 static void fx_xor_r14() { FX_XOR(14); }
1297 static void fx_xor_r15() { FX_XOR(15); }
1299 /* c1-cf(ALT2) - or #n */
1300 #define FX_OR_I(imm) \
1301 uint32 v = SREG | imm; R15++; DREG = v; \
1306 static void fx_or_i1() { FX_OR_I(1); }
1307 static void fx_or_i2() { FX_OR_I(2); }
1308 static void fx_or_i3() { FX_OR_I(3); }
1309 static void fx_or_i4() { FX_OR_I(4); }
1310 static void fx_or_i5() { FX_OR_I(5); }
1311 static void fx_or_i6() { FX_OR_I(6); }
1312 static void fx_or_i7() { FX_OR_I(7); }
1313 static void fx_or_i8() { FX_OR_I(8); }
1314 static void fx_or_i9() { FX_OR_I(9); }
1315 static void fx_or_i10() { FX_OR_I(10); }
1316 static void fx_or_i11() { FX_OR_I(11); }
1317 static void fx_or_i12() { FX_OR_I(12); }
1318 static void fx_or_i13() { FX_OR_I(13); }
1319 static void fx_or_i14() { FX_OR_I(14); }
1320 static void fx_or_i15() { FX_OR_I(15); }
1322 /* c1-cf(ALT3) - xor #n */
1323 #define FX_XOR_I(imm) \
1324 uint32 v = SREG ^ imm; R15++; DREG = v; \
1329 static void fx_xor_i1() { FX_XOR_I(1); }
1330 static void fx_xor_i2() { FX_XOR_I(2); }
1331 static void fx_xor_i3() { FX_XOR_I(3); }
1332 static void fx_xor_i4() { FX_XOR_I(4); }
1333 static void fx_xor_i5() { FX_XOR_I(5); }
1334 static void fx_xor_i6() { FX_XOR_I(6); }
1335 static void fx_xor_i7() { FX_XOR_I(7); }
1336 static void fx_xor_i8() { FX_XOR_I(8); }
1337 static void fx_xor_i9() { FX_XOR_I(9); }
1338 static void fx_xor_i10() { FX_XOR_I(10); }
1339 static void fx_xor_i11() { FX_XOR_I(11); }
1340 static void fx_xor_i12() { FX_XOR_I(12); }
1341 static void fx_xor_i13() { FX_XOR_I(13); }
1342 static void fx_xor_i14() { FX_XOR_I(14); }
1343 static void fx_xor_i15() { FX_XOR_I(15); }
1345 /* d0-de - inc rn - increase by one */
1346 #define FX_INC(reg) \
1347 GSU.avReg[reg] += 1; \
1348 GSU.vSign = GSU.avReg[reg]; \
1349 GSU.vZero = GSU.avReg[reg]; \
1351 static void fx_inc_r0() { FX_INC(0); }
1352 static void fx_inc_r1() { FX_INC(1); }
1353 static void fx_inc_r2() { FX_INC(2); }
1354 static void fx_inc_r3() { FX_INC(3); }
1355 static void fx_inc_r4() { FX_INC(4); }
1356 static void fx_inc_r5() { FX_INC(5); }
1357 static void fx_inc_r6() { FX_INC(6); }
1358 static void fx_inc_r7() { FX_INC(7); }
1359 static void fx_inc_r8() { FX_INC(8); }
1360 static void fx_inc_r9() { FX_INC(9); }
1361 static void fx_inc_r10() { FX_INC(10); }
1362 static void fx_inc_r11() { FX_INC(11); }
1363 static void fx_inc_r12() { FX_INC(12); }
1364 static void fx_inc_r13() { FX_INC(13); }
1365 static void fx_inc_r14() { FX_INC(14); READR14; }
1367 /* df - getc - transfer ROM buffer to color register */
1368 static void fx_getc()
1370 #ifndef FX_DO_ROMBUFFER
1374 uint8 c = GSU.vRomBuffer;
1376 if(GSU.vPlotOptionReg & 0x04)
1377 c = (c&0xf0) | (c>>4);
1378 if(GSU.vPlotOptionReg & 0x08)
1380 GSU.vColorReg &= 0xf0;
1381 GSU.vColorReg |= c & 0x0f;
1384 GSU.vColorReg = USEX8(c);
1389 /* df(ALT2) - ramb - set current RAM bank */
1390 static void fx_ramb()
1392 GSU.vRamBankReg = SREG & (FX_RAM_BANKS-1);
1393 GSU.pvRamBank = GSU.apvRamBank[GSU.vRamBankReg & 0x3];
1398 /* df(ALT3) - romb - set current ROM bank */
1399 static void fx_romb()
1401 GSU.vRomBankReg = USEX8(SREG) & 0x7f;
1402 GSU.pvRomBank = GSU.apvRomBank[GSU.vRomBankReg];
1407 /* e0-ee - dec rn - decrement by one */
1408 #define FX_DEC(reg) \
1409 GSU.avReg[reg] -= 1; \
1410 GSU.vSign = GSU.avReg[reg]; \
1411 GSU.vZero = GSU.avReg[reg]; \
1413 static void fx_dec_r0() { FX_DEC(0); }
1414 static void fx_dec_r1() { FX_DEC(1); }
1415 static void fx_dec_r2() { FX_DEC(2); }
1416 static void fx_dec_r3() { FX_DEC(3); }
1417 static void fx_dec_r4() { FX_DEC(4); }
1418 static void fx_dec_r5() { FX_DEC(5); }
1419 static void fx_dec_r6() { FX_DEC(6); }
1420 static void fx_dec_r7() { FX_DEC(7); }
1421 static void fx_dec_r8() { FX_DEC(8); }
1422 static void fx_dec_r9() { FX_DEC(9); }
1423 static void fx_dec_r10() { FX_DEC(10); }
1424 static void fx_dec_r11() { FX_DEC(11); }
1425 static void fx_dec_r12() { FX_DEC(12); }
1426 static void fx_dec_r13() { FX_DEC(13); }
1427 static void fx_dec_r14() { FX_DEC(14); READR14; }
1429 /* ef - getb - get byte from ROM at address R14 */
1430 static void fx_getb()
1433 #ifndef FX_DO_ROMBUFFER
1434 v = (uint32)ROM(R14);
1436 v = (uint32)GSU.vRomBuffer;
1443 /* ef(ALT1) - getbh - get high-byte from ROM at address R14 */
1444 static void fx_getbh()
1447 #ifndef FX_DO_ROMBUFFER
1449 c = (uint32)ROM(R14);
1451 uint32 c = USEX8(GSU.vRomBuffer);
1453 v = USEX8(SREG) | (c<<8);
1459 /* ef(ALT2) - getbl - get low-byte from ROM at address R14 */
1460 static void fx_getbl()
1463 #ifndef FX_DO_ROMBUFFER
1465 c = (uint32)ROM(R14);
1467 uint32 c = USEX8(GSU.vRomBuffer);
1469 v = (SREG & 0xff00) | c;
1475 /* ef(ALT3) - getbs - get sign extended byte from ROM at address R14 */
1476 static void fx_getbs()
1479 #ifndef FX_DO_ROMBUFFER
1484 v = SEX8(GSU.vRomBuffer);
1491 /* f0-ff - iwt rn,#xx - immediate word transfer to register */
1492 #define FX_IWT(reg) \
1493 uint32 v = PIPE; R15++; FETCHPIPE; R15++; \
1494 v |= USEX8(PIPE) << 8; FETCHPIPE; R15++; \
1495 GSU.avReg[reg] = v; \
1497 static void fx_iwt_r0() { FX_IWT(0); }
1498 static void fx_iwt_r1() { FX_IWT(1); }
1499 static void fx_iwt_r2() { FX_IWT(2); }
1500 static void fx_iwt_r3() { FX_IWT(3); }
1501 static void fx_iwt_r4() { FX_IWT(4); }
1502 static void fx_iwt_r5() { FX_IWT(5); }
1503 static void fx_iwt_r6() { FX_IWT(6); }
1504 static void fx_iwt_r7() { FX_IWT(7); }
1505 static void fx_iwt_r8() { FX_IWT(8); }
1506 static void fx_iwt_r9() { FX_IWT(9); }
1507 static void fx_iwt_r10() { FX_IWT(10); }
1508 static void fx_iwt_r11() { FX_IWT(11); }
1509 static void fx_iwt_r12() { FX_IWT(12); }
1510 static void fx_iwt_r13() { FX_IWT(13); }
1511 static void fx_iwt_r14() { FX_IWT(14); READR14; }
1512 static void fx_iwt_r15() { FX_IWT(15); }
1514 /* f0-ff(ALT1) - lm rn,(xx) - load word from RAM */
1515 #define FX_LM(reg) \
1516 GSU.vLastRamAdr = PIPE; R15++; FETCHPIPE; R15++; \
1517 GSU.vLastRamAdr |= USEX8(PIPE) << 8; FETCHPIPE; R15++; \
1518 GSU.avReg[reg] = RAM(GSU.vLastRamAdr); \
1519 GSU.avReg[reg] |= USEX8(RAM(GSU.vLastRamAdr^1)) << 8; \
1521 static void fx_lm_r0() { FX_LM(0); }
1522 static void fx_lm_r1() { FX_LM(1); }
1523 static void fx_lm_r2() { FX_LM(2); }
1524 static void fx_lm_r3() { FX_LM(3); }
1525 static void fx_lm_r4() { FX_LM(4); }
1526 static void fx_lm_r5() { FX_LM(5); }
1527 static void fx_lm_r6() { FX_LM(6); }
1528 static void fx_lm_r7() { FX_LM(7); }
1529 static void fx_lm_r8() { FX_LM(8); }
1530 static void fx_lm_r9() { FX_LM(9); }
1531 static void fx_lm_r10() { FX_LM(10); }
1532 static void fx_lm_r11() { FX_LM(11); }
1533 static void fx_lm_r12() { FX_LM(12); }
1534 static void fx_lm_r13() { FX_LM(13); }
1535 static void fx_lm_r14() { FX_LM(14); READR14; }
1536 static void fx_lm_r15() { FX_LM(15); }
1538 /* f0-ff(ALT2) - sm (xx),rn - store word in RAM */
1539 /* If rn == r15, is the value of r15 before or after the extra bytes are read? */
1540 #define FX_SM(reg) \
1541 uint32 v = GSU.avReg[reg]; \
1542 GSU.vLastRamAdr = PIPE; R15++; FETCHPIPE; R15++; \
1543 GSU.vLastRamAdr |= USEX8(PIPE) << 8; FETCHPIPE; \
1544 RAM(GSU.vLastRamAdr) = (uint8)v; \
1545 RAM(GSU.vLastRamAdr^1) = (uint8)(v>>8); \
1547 static void fx_sm_r0() { FX_SM(0); }
1548 static void fx_sm_r1() { FX_SM(1); }
1549 static void fx_sm_r2() { FX_SM(2); }
1550 static void fx_sm_r3() { FX_SM(3); }
1551 static void fx_sm_r4() { FX_SM(4); }
1552 static void fx_sm_r5() { FX_SM(5); }
1553 static void fx_sm_r6() { FX_SM(6); }
1554 static void fx_sm_r7() { FX_SM(7); }
1555 static void fx_sm_r8() { FX_SM(8); }
1556 static void fx_sm_r9() { FX_SM(9); }
1557 static void fx_sm_r10() { FX_SM(10); }
1558 static void fx_sm_r11() { FX_SM(11); }
1559 static void fx_sm_r12() { FX_SM(12); }
1560 static void fx_sm_r13() { FX_SM(13); }
1561 static void fx_sm_r14() { FX_SM(14); }
1562 static void fx_sm_r15() { FX_SM(15); }
1564 /*** GSU executions functions ***/
1566 static uint32 fx_run(uint32 nInstructions)
1568 GSU.vCounter = nInstructions;
1570 while(GSU.vCounter-- > 0) {
1574 #ifndef FX_ADDRESS_CHECK
1575 GSU.vPipeAdr = USEX16(R15-1) | (USEX8(GSU.vPrgBankReg)<<16);
1578 return nInstructions - GSU.vInstCount;
1581 static uint32 fx_run_to_breakpoint(uint32 nInstructions)
1583 uint32 vCounter = 0;
1584 while(TF(G) && vCounter < nInstructions)
1588 if(USEX16(R15) == GSU.vBreakPoint)
1590 GSU.vErrorCode = FX_BREAKPOINT;
1595 #ifndef FX_ADDRESS_CHECK
1596 GSU.vPipeAdr = USEX16(R15-1) | (USEX8(GSU.vPrgBankReg)<<16);
1602 static uint32 fx_step_over(uint32 nInstructions)
1604 uint32 vCounter = 0;
1605 while(TF(G) && vCounter < nInstructions)
1609 if(USEX16(R15) == GSU.vBreakPoint)
1611 GSU.vErrorCode = FX_BREAKPOINT;
1614 if(USEX16(R15) == GSU.vStepPoint)
1618 #ifndef FX_ADDRESS_CHECK
1619 GSU.vPipeAdr = USEX16(R15-1) | (USEX8(GSU.vPrgBankReg)<<16);
1625 #ifdef FX_FUNCTION_TABLE
1626 uint32 (*FX_FUNCTION_TABLE[])(uint32) =
1628 uint32 (*fx_apfFunctionTable[])(uint32) =
1632 &fx_run_to_breakpoint,
1636 /*** Special table for the different plot configurations ***/
1638 #ifdef FX_PLOT_TABLE
1639 void (*FX_PLOT_TABLE[])() =
1641 void (*fx_apfPlotTable[])() =
1644 &fx_plot_2bit, &fx_plot_4bit, &fx_plot_4bit, &fx_plot_8bit, &fx_plot_obj,
1645 &fx_rpix_2bit, &fx_rpix_4bit, &fx_rpix_4bit, &fx_rpix_8bit, &fx_rpix_obj,
1648 /*** Opcode table ***/
1650 #ifdef FX_OPCODE_TABLE
1651 void (*FX_OPCODE_TABLE[])() =
1653 void (*fx_apfOpcodeTable[])() =
1660 &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt,
1661 &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs,
1663 &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7,
1664 &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15,
1666 &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7,
1667 &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15,
1669 &fx_stw_r0, &fx_stw_r1, &fx_stw_r2, &fx_stw_r3, &fx_stw_r4, &fx_stw_r5, &fx_stw_r6, &fx_stw_r7,
1670 &fx_stw_r8, &fx_stw_r9, &fx_stw_r10, &fx_stw_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3,
1672 &fx_ldw_r0, &fx_ldw_r1, &fx_ldw_r2, &fx_ldw_r3, &fx_ldw_r4, &fx_ldw_r5, &fx_ldw_r6, &fx_ldw_r7,
1673 &fx_ldw_r8, &fx_ldw_r9, &fx_ldw_r10, &fx_ldw_r11, &fx_plot_2bit,&fx_swap, &fx_color, &fx_not,
1675 &fx_add_r0, &fx_add_r1, &fx_add_r2, &fx_add_r3, &fx_add_r4, &fx_add_r5, &fx_add_r6, &fx_add_r7,
1676 &fx_add_r8, &fx_add_r9, &fx_add_r10, &fx_add_r11, &fx_add_r12, &fx_add_r13, &fx_add_r14, &fx_add_r15,
1678 &fx_sub_r0, &fx_sub_r1, &fx_sub_r2, &fx_sub_r3, &fx_sub_r4, &fx_sub_r5, &fx_sub_r6, &fx_sub_r7,
1679 &fx_sub_r8, &fx_sub_r9, &fx_sub_r10, &fx_sub_r11, &fx_sub_r12, &fx_sub_r13, &fx_sub_r14, &fx_sub_r15,
1681 &fx_merge, &fx_and_r1, &fx_and_r2, &fx_and_r3, &fx_and_r4, &fx_and_r5, &fx_and_r6, &fx_and_r7,
1682 &fx_and_r8, &fx_and_r9, &fx_and_r10, &fx_and_r11, &fx_and_r12, &fx_and_r13, &fx_and_r14, &fx_and_r15,
1684 &fx_mult_r0, &fx_mult_r1, &fx_mult_r2, &fx_mult_r3, &fx_mult_r4, &fx_mult_r5, &fx_mult_r6, &fx_mult_r7,
1685 &fx_mult_r8, &fx_mult_r9, &fx_mult_r10, &fx_mult_r11, &fx_mult_r12, &fx_mult_r13, &fx_mult_r14, &fx_mult_r15,
1687 &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_asr, &fx_ror,
1688 &fx_jmp_r8, &fx_jmp_r9, &fx_jmp_r10, &fx_jmp_r11, &fx_jmp_r12, &fx_jmp_r13, &fx_lob, &fx_fmult,
1690 &fx_ibt_r0, &fx_ibt_r1, &fx_ibt_r2, &fx_ibt_r3, &fx_ibt_r4, &fx_ibt_r5, &fx_ibt_r6, &fx_ibt_r7,
1691 &fx_ibt_r8, &fx_ibt_r9, &fx_ibt_r10, &fx_ibt_r11, &fx_ibt_r12, &fx_ibt_r13, &fx_ibt_r14, &fx_ibt_r15,
1693 &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7,
1694 &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15,
1696 &fx_hib, &fx_or_r1, &fx_or_r2, &fx_or_r3, &fx_or_r4, &fx_or_r5, &fx_or_r6, &fx_or_r7,
1697 &fx_or_r8, &fx_or_r9, &fx_or_r10, &fx_or_r11, &fx_or_r12, &fx_or_r13, &fx_or_r14, &fx_or_r15,
1699 &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7,
1700 &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_getc,
1702 &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7,
1703 &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getb,
1705 &fx_iwt_r0, &fx_iwt_r1, &fx_iwt_r2, &fx_iwt_r3, &fx_iwt_r4, &fx_iwt_r5, &fx_iwt_r6, &fx_iwt_r7,
1706 &fx_iwt_r8, &fx_iwt_r9, &fx_iwt_r10, &fx_iwt_r11, &fx_iwt_r12, &fx_iwt_r13, &fx_iwt_r14, &fx_iwt_r15,
1713 &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt,
1714 &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs,
1716 &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7,
1717 &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15,
1719 &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7,
1720 &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15,
1722 &fx_stb_r0, &fx_stb_r1, &fx_stb_r2, &fx_stb_r3, &fx_stb_r4, &fx_stb_r5, &fx_stb_r6, &fx_stb_r7,
1723 &fx_stb_r8, &fx_stb_r9, &fx_stb_r10, &fx_stb_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3,
1725 &fx_ldb_r0, &fx_ldb_r1, &fx_ldb_r2, &fx_ldb_r3, &fx_ldb_r4, &fx_ldb_r5, &fx_ldb_r6, &fx_ldb_r7,
1726 &fx_ldb_r8, &fx_ldb_r9, &fx_ldb_r10, &fx_ldb_r11, &fx_rpix_2bit,&fx_swap, &fx_cmode, &fx_not,
1728 &fx_adc_r0, &fx_adc_r1, &fx_adc_r2, &fx_adc_r3, &fx_adc_r4, &fx_adc_r5, &fx_adc_r6, &fx_adc_r7,
1729 &fx_adc_r8, &fx_adc_r9, &fx_adc_r10, &fx_adc_r11, &fx_adc_r12, &fx_adc_r13, &fx_adc_r14, &fx_adc_r15,
1731 &fx_sbc_r0, &fx_sbc_r1, &fx_sbc_r2, &fx_sbc_r3, &fx_sbc_r4, &fx_sbc_r5, &fx_sbc_r6, &fx_sbc_r7,
1732 &fx_sbc_r8, &fx_sbc_r9, &fx_sbc_r10, &fx_sbc_r11, &fx_sbc_r12, &fx_sbc_r13, &fx_sbc_r14, &fx_sbc_r15,
1734 &fx_merge, &fx_bic_r1, &fx_bic_r2, &fx_bic_r3, &fx_bic_r4, &fx_bic_r5, &fx_bic_r6, &fx_bic_r7,
1735 &fx_bic_r8, &fx_bic_r9, &fx_bic_r10, &fx_bic_r11, &fx_bic_r12, &fx_bic_r13, &fx_bic_r14, &fx_bic_r15,
1737 &fx_umult_r0,&fx_umult_r1,&fx_umult_r2, &fx_umult_r3, &fx_umult_r4, &fx_umult_r5, &fx_umult_r6, &fx_umult_r7,
1738 &fx_umult_r8,&fx_umult_r9,&fx_umult_r10,&fx_umult_r11,&fx_umult_r12,&fx_umult_r13,&fx_umult_r14,&fx_umult_r15,
1740 &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_div2, &fx_ror,
1741 &fx_ljmp_r8, &fx_ljmp_r9, &fx_ljmp_r10, &fx_ljmp_r11, &fx_ljmp_r12, &fx_ljmp_r13, &fx_lob, &fx_lmult,
1743 &fx_lms_r0, &fx_lms_r1, &fx_lms_r2, &fx_lms_r3, &fx_lms_r4, &fx_lms_r5, &fx_lms_r6, &fx_lms_r7,
1744 &fx_lms_r8, &fx_lms_r9, &fx_lms_r10, &fx_lms_r11, &fx_lms_r12, &fx_lms_r13, &fx_lms_r14, &fx_lms_r15,
1746 &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7,
1747 &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15,
1749 &fx_hib, &fx_xor_r1, &fx_xor_r2, &fx_xor_r3, &fx_xor_r4, &fx_xor_r5, &fx_xor_r6, &fx_xor_r7,
1750 &fx_xor_r8, &fx_xor_r9, &fx_xor_r10, &fx_xor_r11, &fx_xor_r12, &fx_xor_r13, &fx_xor_r14, &fx_xor_r15,
1752 &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7,
1753 &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_getc,
1755 &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7,
1756 &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbh,
1758 &fx_lm_r0, &fx_lm_r1, &fx_lm_r2, &fx_lm_r3, &fx_lm_r4, &fx_lm_r5, &fx_lm_r6, &fx_lm_r7,
1759 &fx_lm_r8, &fx_lm_r9, &fx_lm_r10, &fx_lm_r11, &fx_lm_r12, &fx_lm_r13, &fx_lm_r14, &fx_lm_r15,
1766 &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt,
1767 &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs,
1769 &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7,
1770 &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15,
1772 &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7,
1773 &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15,
1775 &fx_stw_r0, &fx_stw_r1, &fx_stw_r2, &fx_stw_r3, &fx_stw_r4, &fx_stw_r5, &fx_stw_r6, &fx_stw_r7,
1776 &fx_stw_r8, &fx_stw_r9, &fx_stw_r10, &fx_stw_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3,
1778 &fx_ldw_r0, &fx_ldw_r1, &fx_ldw_r2, &fx_ldw_r3, &fx_ldw_r4, &fx_ldw_r5, &fx_ldw_r6, &fx_ldw_r7,
1779 &fx_ldw_r8, &fx_ldw_r9, &fx_ldw_r10, &fx_ldw_r11, &fx_plot_2bit,&fx_swap, &fx_color, &fx_not,
1781 &fx_add_i0, &fx_add_i1, &fx_add_i2, &fx_add_i3, &fx_add_i4, &fx_add_i5, &fx_add_i6, &fx_add_i7,
1782 &fx_add_i8, &fx_add_i9, &fx_add_i10, &fx_add_i11, &fx_add_i12, &fx_add_i13, &fx_add_i14, &fx_add_i15,
1784 &fx_sub_i0, &fx_sub_i1, &fx_sub_i2, &fx_sub_i3, &fx_sub_i4, &fx_sub_i5, &fx_sub_i6, &fx_sub_i7,
1785 &fx_sub_i8, &fx_sub_i9, &fx_sub_i10, &fx_sub_i11, &fx_sub_i12, &fx_sub_i13, &fx_sub_i14, &fx_sub_i15,
1787 &fx_merge, &fx_and_i1, &fx_and_i2, &fx_and_i3, &fx_and_i4, &fx_and_i5, &fx_and_i6, &fx_and_i7,
1788 &fx_and_i8, &fx_and_i9, &fx_and_i10, &fx_and_i11, &fx_and_i12, &fx_and_i13, &fx_and_i14, &fx_and_i15,
1790 &fx_mult_i0, &fx_mult_i1, &fx_mult_i2, &fx_mult_i3, &fx_mult_i4, &fx_mult_i5, &fx_mult_i6, &fx_mult_i7,
1791 &fx_mult_i8, &fx_mult_i9, &fx_mult_i10, &fx_mult_i11, &fx_mult_i12, &fx_mult_i13, &fx_mult_i14, &fx_mult_i15,
1793 &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_asr, &fx_ror,
1794 &fx_jmp_r8, &fx_jmp_r9, &fx_jmp_r10, &fx_jmp_r11, &fx_jmp_r12, &fx_jmp_r13, &fx_lob, &fx_fmult,
1796 &fx_sms_r0, &fx_sms_r1, &fx_sms_r2, &fx_sms_r3, &fx_sms_r4, &fx_sms_r5, &fx_sms_r6, &fx_sms_r7,
1797 &fx_sms_r8, &fx_sms_r9, &fx_sms_r10, &fx_sms_r11, &fx_sms_r12, &fx_sms_r13, &fx_sms_r14, &fx_sms_r15,
1799 &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7,
1800 &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15,
1802 &fx_hib, &fx_or_i1, &fx_or_i2, &fx_or_i3, &fx_or_i4, &fx_or_i5, &fx_or_i6, &fx_or_i7,
1803 &fx_or_i8, &fx_or_i9, &fx_or_i10, &fx_or_i11, &fx_or_i12, &fx_or_i13, &fx_or_i14, &fx_or_i15,
1805 &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7,
1806 &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_ramb,
1808 &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7,
1809 &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbl,
1811 &fx_sm_r0, &fx_sm_r1, &fx_sm_r2, &fx_sm_r3, &fx_sm_r4, &fx_sm_r5, &fx_sm_r6, &fx_sm_r7,
1812 &fx_sm_r8, &fx_sm_r9, &fx_sm_r10, &fx_sm_r11, &fx_sm_r12, &fx_sm_r13, &fx_sm_r14, &fx_sm_r15,
1819 &fx_stop, &fx_nop, &fx_cache, &fx_lsr, &fx_rol, &fx_bra, &fx_bge, &fx_blt,
1820 &fx_bne, &fx_beq, &fx_bpl, &fx_bmi, &fx_bcc, &fx_bcs, &fx_bvc, &fx_bvs,
1822 &fx_to_r0, &fx_to_r1, &fx_to_r2, &fx_to_r3, &fx_to_r4, &fx_to_r5, &fx_to_r6, &fx_to_r7,
1823 &fx_to_r8, &fx_to_r9, &fx_to_r10, &fx_to_r11, &fx_to_r12, &fx_to_r13, &fx_to_r14, &fx_to_r15,
1825 &fx_with_r0, &fx_with_r1, &fx_with_r2, &fx_with_r3, &fx_with_r4, &fx_with_r5, &fx_with_r6, &fx_with_r7,
1826 &fx_with_r8, &fx_with_r9, &fx_with_r10, &fx_with_r11, &fx_with_r12, &fx_with_r13, &fx_with_r14, &fx_with_r15,
1828 &fx_stb_r0, &fx_stb_r1, &fx_stb_r2, &fx_stb_r3, &fx_stb_r4, &fx_stb_r5, &fx_stb_r6, &fx_stb_r7,
1829 &fx_stb_r8, &fx_stb_r9, &fx_stb_r10, &fx_stb_r11, &fx_loop, &fx_alt1, &fx_alt2, &fx_alt3,
1831 &fx_ldb_r0, &fx_ldb_r1, &fx_ldb_r2, &fx_ldb_r3, &fx_ldb_r4, &fx_ldb_r5, &fx_ldb_r6, &fx_ldb_r7,
1832 &fx_ldb_r8, &fx_ldb_r9, &fx_ldb_r10, &fx_ldb_r11, &fx_rpix_2bit,&fx_swap, &fx_cmode, &fx_not,
1834 &fx_adc_i0, &fx_adc_i1, &fx_adc_i2, &fx_adc_i3, &fx_adc_i4, &fx_adc_i5, &fx_adc_i6, &fx_adc_i7,
1835 &fx_adc_i8, &fx_adc_i9, &fx_adc_i10, &fx_adc_i11, &fx_adc_i12, &fx_adc_i13, &fx_adc_i14, &fx_adc_i15,
1837 &fx_cmp_r0, &fx_cmp_r1, &fx_cmp_r2, &fx_cmp_r3, &fx_cmp_r4, &fx_cmp_r5, &fx_cmp_r6, &fx_cmp_r7,
1838 &fx_cmp_r8, &fx_cmp_r9, &fx_cmp_r10, &fx_cmp_r11, &fx_cmp_r12, &fx_cmp_r13, &fx_cmp_r14, &fx_cmp_r15,
1840 &fx_merge, &fx_bic_i1, &fx_bic_i2, &fx_bic_i3, &fx_bic_i4, &fx_bic_i5, &fx_bic_i6, &fx_bic_i7,
1841 &fx_bic_i8, &fx_bic_i9, &fx_bic_i10, &fx_bic_i11, &fx_bic_i12, &fx_bic_i13, &fx_bic_i14, &fx_bic_i15,
1843 &fx_umult_i0,&fx_umult_i1,&fx_umult_i2, &fx_umult_i3, &fx_umult_i4, &fx_umult_i5, &fx_umult_i6, &fx_umult_i7,
1844 &fx_umult_i8,&fx_umult_i9,&fx_umult_i10,&fx_umult_i11,&fx_umult_i12,&fx_umult_i13,&fx_umult_i14,&fx_umult_i15,
1846 &fx_sbk, &fx_link_i1, &fx_link_i2, &fx_link_i3, &fx_link_i4, &fx_sex, &fx_div2, &fx_ror,
1847 &fx_ljmp_r8, &fx_ljmp_r9, &fx_ljmp_r10, &fx_ljmp_r11, &fx_ljmp_r12, &fx_ljmp_r13, &fx_lob, &fx_lmult,
1849 &fx_lms_r0, &fx_lms_r1, &fx_lms_r2, &fx_lms_r3, &fx_lms_r4, &fx_lms_r5, &fx_lms_r6, &fx_lms_r7,
1850 &fx_lms_r8, &fx_lms_r9, &fx_lms_r10, &fx_lms_r11, &fx_lms_r12, &fx_lms_r13, &fx_lms_r14, &fx_lms_r15,
1852 &fx_from_r0, &fx_from_r1, &fx_from_r2, &fx_from_r3, &fx_from_r4, &fx_from_r5, &fx_from_r6, &fx_from_r7,
1853 &fx_from_r8, &fx_from_r9, &fx_from_r10, &fx_from_r11, &fx_from_r12, &fx_from_r13, &fx_from_r14, &fx_from_r15,
1855 &fx_hib, &fx_xor_i1, &fx_xor_i2, &fx_xor_i3, &fx_xor_i4, &fx_xor_i5, &fx_xor_i6, &fx_xor_i7,
1856 &fx_xor_i8, &fx_xor_i9, &fx_xor_i10, &fx_xor_i11, &fx_xor_i12, &fx_xor_i13, &fx_xor_i14, &fx_xor_i15,
1858 &fx_inc_r0, &fx_inc_r1, &fx_inc_r2, &fx_inc_r3, &fx_inc_r4, &fx_inc_r5, &fx_inc_r6, &fx_inc_r7,
1859 &fx_inc_r8, &fx_inc_r9, &fx_inc_r10, &fx_inc_r11, &fx_inc_r12, &fx_inc_r13, &fx_inc_r14, &fx_romb,
1861 &fx_dec_r0, &fx_dec_r1, &fx_dec_r2, &fx_dec_r3, &fx_dec_r4, &fx_dec_r5, &fx_dec_r6, &fx_dec_r7,
1862 &fx_dec_r8, &fx_dec_r9, &fx_dec_r10, &fx_dec_r11, &fx_dec_r12, &fx_dec_r13, &fx_dec_r14, &fx_getbs,
1864 &fx_lm_r0, &fx_lm_r1, &fx_lm_r2, &fx_lm_r3, &fx_lm_r4, &fx_lm_r5, &fx_lm_r6, &fx_lm_r7,
1865 &fx_lm_r8, &fx_lm_r9, &fx_lm_r10, &fx_lm_r11, &fx_lm_r12, &fx_lm_r13, &fx_lm_r14, &fx_lm_r15,