2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #define GEN_FLAG_CODE32_SHIFT 0
22 #define GEN_FLAG_ADDSEG_SHIFT 1
23 #define GEN_FLAG_SS32_SHIFT 2
24 #define GEN_FLAG_VM_SHIFT 3
25 #define GEN_FLAG_ST_SHIFT 4
26 #define GEN_FLAG_TF_SHIFT 8 /* same position as eflags */
27 #define GEN_FLAG_CPL_SHIFT 9
28 #define GEN_FLAG_IOPL_SHIFT 12 /* same position as eflags */
30 struct TranslationBlock;
31 int cpu_x86_gen_code(struct TranslationBlock *tb,
32 int max_code_size, int *gen_code_size_ptr);
33 int cpu_x86_search_pc(struct TranslationBlock *tb,
34 uint32_t *found_pc, unsigned long searched_pc);
35 void cpu_x86_tblocks_init(void);
37 int page_unprotect(unsigned long address);
39 #define CODE_GEN_MAX_SIZE 65536
40 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
42 #define CODE_GEN_HASH_BITS 15
43 #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
45 /* maximum total translate dcode allocated */
46 #define CODE_GEN_BUFFER_SIZE (2048 * 1024)
47 //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
49 #if defined(__powerpc__)
50 #define USE_DIRECT_JUMP
53 typedef struct TranslationBlock {
54 unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
55 unsigned long cs_base; /* CS base for this block */
56 unsigned int flags; /* flags defining in which context the code was generated */
57 uint16_t size; /* size of target code for this block (1 <=
58 size <= TARGET_PAGE_SIZE) */
59 uint8_t *tc_ptr; /* pointer to the translated code */
60 struct TranslationBlock *hash_next; /* next matching block */
61 struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */
62 /* the following data are used to directly call another TB from
63 the code of this one. */
64 uint16_t tb_next_offset[2]; /* offset of original jump target */
65 #ifdef USE_DIRECT_JUMP
66 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
68 uint32_t tb_next[2]; /* address of jump generated code */
70 /* list of TBs jumping to this one. This is a circular list using
71 the two least significant bits of the pointers to tell what is
72 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
74 struct TranslationBlock *jmp_next[2];
75 struct TranslationBlock *jmp_first;
78 static inline unsigned int tb_hash_func(unsigned long pc)
80 return pc & (CODE_GEN_HASH_SIZE - 1);
83 TranslationBlock *tb_alloc(unsigned long pc);
85 void tb_link(TranslationBlock *tb);
87 extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
89 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
90 extern uint8_t *code_gen_ptr;
92 /* find a translation block in the translation cache. If not found,
93 return NULL and the pointer to the last element of the list in pptb */
94 static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
96 unsigned long cs_base,
99 TranslationBlock **ptb, *tb;
102 h = tb_hash_func(pc);
108 if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
110 ptb = &tb->hash_next;
116 #if defined(__powerpc__)
118 static inline void tb_set_jmp_target(TranslationBlock *tb,
119 int n, unsigned long addr)
122 unsigned long offset;
124 offset = (unsigned long)(tb->tc_ptr + tb->tb_jmp_offset[n]);
126 /* patch the branch destination */
127 ptr = (uint32_t *)offset;
129 val = (val & ~0x03fffffc) | ((addr - offset) & 0x03fffffc);
132 asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
133 asm volatile ("sync" : : : "memory");
134 asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
135 asm volatile ("sync" : : : "memory");
136 asm volatile ("isync" : : : "memory");
141 /* set the jump target */
142 static inline void tb_set_jmp_target(TranslationBlock *tb,
143 int n, unsigned long addr)
145 tb->tb_next[n] = addr;
150 static inline void tb_add_jump(TranslationBlock *tb, int n,
151 TranslationBlock *tb_next)
153 /* NOTE: this test is only needed for thread safety */
154 if (!tb->jmp_next[n]) {
155 /* patch the native jump address */
156 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
158 /* add in TB jmp circular list */
159 tb->jmp_next[n] = tb_next->jmp_first;
160 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
164 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
167 #define offsetof(type, field) ((size_t) &((type *)0)->field)
171 static inline int testandset (int *p)
174 __asm__ __volatile__ (
182 : "r" (p), "r" (1), "r" (0)
189 static inline int testandset (int *p)
194 __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
195 : "=q" (ret), "=m" (*p), "=a" (readval)
196 : "r" (1), "m" (*p), "a" (0)
203 static inline int testandset (int *p)
207 __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
210 : "r" (1), "a" (p), "0" (*p)
217 static inline int testandset (int *p)
222 __asm__ __volatile__ ("0: mov 1,%2\n"
229 : "=r" (ret), "=m" (*p), "=r" (one)
236 static inline int testandset (int *p)
240 __asm__ __volatile__("ldstub [%1], %0"
245 return (ret ? 1 : 0);
249 typedef int spinlock_t;
251 #define SPIN_LOCK_UNLOCKED 0
253 static inline void spin_lock(spinlock_t *lock)
255 while (testandset(lock));
258 static inline void spin_unlock(spinlock_t *lock)
263 static inline int spin_trylock(spinlock_t *lock)
265 return !testandset(lock);
268 extern spinlock_t tb_lock;