2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
24 /* is_jmp field values */
25 #define DISAS_NEXT 0 /* next instruction can be analyzed */
26 #define DISAS_JUMP 1 /* only pc was modified dynamically */
27 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
30 struct TranslationBlock;
32 /* XXX: make safe guess about sizes */
33 #define MAX_OP_PER_INSTR 32
34 #define OPC_BUF_SIZE 512
35 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
37 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
39 extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
40 extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
41 extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
42 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
44 #if defined(TARGET_I386)
46 #define GEN_FLAG_CODE32_SHIFT 0
47 #define GEN_FLAG_ADDSEG_SHIFT 1
48 #define GEN_FLAG_SS32_SHIFT 2
49 #define GEN_FLAG_VM_SHIFT 3
50 #define GEN_FLAG_ST_SHIFT 4
51 #define GEN_FLAG_TF_SHIFT 8 /* same position as eflags */
52 #define GEN_FLAG_CPL_SHIFT 9
53 #define GEN_FLAG_IOPL_SHIFT 12 /* same position as eflags */
60 int gen_intermediate_code(struct TranslationBlock *tb, int search_pc);
61 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
62 int cpu_gen_code(struct TranslationBlock *tb,
63 int max_code_size, int *gen_code_size_ptr);
64 int cpu_search_pc(struct TranslationBlock *tb,
65 uint32_t *found_pc, unsigned long searched_pc);
66 void cpu_exec_init(void);
67 int page_unprotect(unsigned long address);
69 #define CODE_GEN_MAX_SIZE 65536
70 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
72 #define CODE_GEN_HASH_BITS 15
73 #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
75 /* maximum total translate dcode allocated */
76 #define CODE_GEN_BUFFER_SIZE (2048 * 1024)
77 //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
79 #if defined(__powerpc__)
80 #define USE_DIRECT_JUMP
83 typedef struct TranslationBlock {
84 unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
85 unsigned long cs_base; /* CS base for this block */
86 unsigned int flags; /* flags defining in which context the code was generated */
87 uint16_t size; /* size of target code for this block (1 <=
88 size <= TARGET_PAGE_SIZE) */
89 uint8_t *tc_ptr; /* pointer to the translated code */
90 struct TranslationBlock *hash_next; /* next matching block */
91 struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */
92 /* the following data are used to directly call another TB from
93 the code of this one. */
94 uint16_t tb_next_offset[2]; /* offset of original jump target */
95 #ifdef USE_DIRECT_JUMP
96 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
98 uint32_t tb_next[2]; /* address of jump generated code */
100 /* list of TBs jumping to this one. This is a circular list using
101 the two least significant bits of the pointers to tell what is
102 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
104 struct TranslationBlock *jmp_next[2];
105 struct TranslationBlock *jmp_first;
108 static inline unsigned int tb_hash_func(unsigned long pc)
110 return pc & (CODE_GEN_HASH_SIZE - 1);
113 TranslationBlock *tb_alloc(unsigned long pc);
115 void tb_link(TranslationBlock *tb);
117 extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
119 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
120 extern uint8_t *code_gen_ptr;
122 /* find a translation block in the translation cache. If not found,
123 return NULL and the pointer to the last element of the list in pptb */
124 static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
126 unsigned long cs_base,
129 TranslationBlock **ptb, *tb;
132 h = tb_hash_func(pc);
138 if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
140 ptb = &tb->hash_next;
146 #if defined(__powerpc__)
148 static inline void tb_set_jmp_target(TranslationBlock *tb,
149 int n, unsigned long addr)
152 unsigned long offset;
154 offset = (unsigned long)(tb->tc_ptr + tb->tb_jmp_offset[n]);
156 /* patch the branch destination */
157 ptr = (uint32_t *)offset;
159 val = (val & ~0x03fffffc) | ((addr - offset) & 0x03fffffc);
162 asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
163 asm volatile ("sync" : : : "memory");
164 asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
165 asm volatile ("sync" : : : "memory");
166 asm volatile ("isync" : : : "memory");
171 /* set the jump target */
172 static inline void tb_set_jmp_target(TranslationBlock *tb,
173 int n, unsigned long addr)
175 tb->tb_next[n] = addr;
180 static inline void tb_add_jump(TranslationBlock *tb, int n,
181 TranslationBlock *tb_next)
183 /* NOTE: this test is only needed for thread safety */
184 if (!tb->jmp_next[n]) {
185 /* patch the native jump address */
186 tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
188 /* add in TB jmp circular list */
189 tb->jmp_next[n] = tb_next->jmp_first;
190 tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
194 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
197 #define offsetof(type, field) ((size_t) &((type *)0)->field)
200 #if defined(__powerpc__)
202 /* on PowerPC we patch the jump instruction directly */
203 #define JUMP_TB(tbparam, n, eip)\
205 static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
206 asm volatile ("b %0" : : "i" (&__op_jmp ## n));\
208 T0 = (long)(tbparam) + (n);\
214 /* jump to next block operations (more portable code, does not need
215 cache flushing, but slower because of indirect jump) */
216 #define JUMP_TB(tbparam, n, eip)\
218 static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
219 goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
221 T0 = (long)(tbparam) + (n);\
228 static inline int testandset (int *p)
231 __asm__ __volatile__ (
239 : "r" (p), "r" (1), "r" (0)
246 static inline int testandset (int *p)
251 __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
252 : "=q" (ret), "=m" (*p), "=a" (readval)
253 : "r" (1), "m" (*p), "a" (0)
260 static inline int testandset (int *p)
264 __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
267 : "r" (1), "a" (p), "0" (*p)
274 static inline int testandset (int *p)
279 __asm__ __volatile__ ("0: mov 1,%2\n"
286 : "=r" (ret), "=m" (*p), "=r" (one)
293 static inline int testandset (int *p)
297 __asm__ __volatile__("ldstub [%1], %0"
302 return (ret ? 1 : 0);
307 static inline int testandset (int *spinlock)
309 register unsigned int ret;
310 __asm__ __volatile__("swp %0, %1, [%2]"
312 : "0"(1), "r"(spinlock));
318 typedef int spinlock_t;
320 #define SPIN_LOCK_UNLOCKED 0
322 static inline void spin_lock(spinlock_t *lock)
324 while (testandset(lock));
327 static inline void spin_unlock(spinlock_t *lock)
332 static inline int spin_trylock(spinlock_t *lock)
334 return !testandset(lock);
337 extern spinlock_t tb_lock;