2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include "exec-i386.h"
24 //#define DEBUG_SIGNAL
26 /* main execution loop */
28 int cpu_x86_exec(CPUX86State *env1)
30 int saved_T0, saved_T1, saved_A0;
31 CPUX86State *saved_env;
59 int code_gen_size, ret;
60 void (*gen_func)(void);
61 TranslationBlock *tb, **ptb;
62 uint8_t *tc_ptr, *cs_base, *pc;
65 /* first we save global registers */
73 EAX = env->regs[R_EAX];
77 ECX = env->regs[R_ECX];
81 EDX = env->regs[R_EDX];
85 EBX = env->regs[R_EBX];
89 ESP = env->regs[R_ESP];
93 EBP = env->regs[R_EBP];
97 ESI = env->regs[R_ESI];
101 EDI = env->regs[R_EDI];
104 /* we also save i7 because longjmp may not restore it */
105 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
108 /* put eflags in CPU temporary format */
109 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
110 DF = 1 - (2 * ((env->eflags >> 10) & 1));
111 CC_OP = CC_OP_EFLAGS;
112 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
113 env->interrupt_request = 0;
115 /* prepare setjmp context for exception handling */
116 if (setjmp(env->jmp_env) == 0) {
117 T0 = 0; /* force lookup of first TB */
120 /* g1 can be modified by some libc? functions */
123 if (env->interrupt_request) {
124 env->exception_index = EXCP_INTERRUPT;
129 /* XXX: save all volatile state in cpu state */
130 /* restore flags in standard format */
131 env->regs[R_EAX] = EAX;
132 env->regs[R_EBX] = EBX;
133 env->regs[R_ECX] = ECX;
134 env->regs[R_EDX] = EDX;
135 env->regs[R_ESI] = ESI;
136 env->regs[R_EDI] = EDI;
137 env->regs[R_EBP] = EBP;
138 env->regs[R_ESP] = ESP;
139 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
140 cpu_x86_dump_state(env, logfile, 0);
141 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
144 /* we compute the CPU state. We assume it will not
145 change during the whole generated block. */
146 flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
147 flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
148 flags |= (((unsigned long)env->seg_cache[R_DS].base |
149 (unsigned long)env->seg_cache[R_ES].base |
150 (unsigned long)env->seg_cache[R_SS].base) != 0) <<
151 GEN_FLAG_ADDSEG_SHIFT;
152 if (!(env->eflags & VM_MASK)) {
153 flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
155 /* NOTE: a dummy CPL is kept */
156 flags |= (1 << GEN_FLAG_VM_SHIFT);
157 flags |= (3 << GEN_FLAG_CPL_SHIFT);
159 flags |= (env->eflags & (IOPL_MASK | TF_MASK));
160 cs_base = env->seg_cache[R_CS].base;
161 pc = cs_base + env->eip;
162 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
166 /* if no translated code available, then translate it now */
167 tb = tb_alloc((unsigned long)pc);
169 /* flush must be done */
171 /* cannot fail at this point */
172 tb = tb_alloc((unsigned long)pc);
173 /* don't forget to invalidate previous TB info */
174 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
177 tc_ptr = code_gen_ptr;
179 tb->cs_base = (unsigned long)cs_base;
181 ret = cpu_x86_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
182 /* if invalid instruction, signal it */
184 /* NOTE: the tb is allocated but not linked, so we
186 spin_unlock(&tb_lock);
187 raise_exception(EXCP06_ILLOP);
190 tb->hash_next = NULL;
192 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
193 spin_unlock(&tb_lock);
197 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
198 (long)tb->tc_ptr, (long)tb->pc,
199 lookup_symbol((void *)tb->pc));
205 /* see if we can patch the calling TB */
206 if (T0 != 0 && !(env->eflags & TF_MASK)) {
208 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
209 spin_unlock(&tb_lock);
213 /* execute the generated code */
214 gen_func = (void *)tc_ptr;
215 #if defined(__sparc__)
216 __asm__ __volatile__("call %0\n\t"
220 : "i0", "i1", "i2", "i3", "i4", "i5");
221 #elif defined(__arm__)
222 asm volatile ("mov pc, %0\n\t"
223 ".global exec_loop\n\t"
227 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
233 ret = env->exception_index;
235 /* restore flags in standard format */
236 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
238 /* restore global registers */
264 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
273 void cpu_x86_interrupt(CPUX86State *s)
275 s->interrupt_request = 1;
279 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
281 CPUX86State *saved_env;
285 if (env->eflags & VM_MASK) {
288 sc = &env->seg_cache[seg_reg];
289 /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
290 so we must load them here */
291 sc->base = (void *)(selector << 4);
294 env->segs[seg_reg] = selector;
296 load_seg(seg_reg, selector, 0);
301 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
303 CPUX86State *saved_env;
308 helper_fsave(ptr, data32);
313 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
315 CPUX86State *saved_env;
320 helper_frstor(ptr, data32);
335 #include <sys/ucontext.h>
337 /* 'pc' is the host PC at which the exception was raised. 'address' is
338 the effective address of the memory exception. 'is_write' is 1 if a
339 write caused the exception and otherwise 0'. 'old_set' is the
340 signal set which should be restored */
341 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
342 int is_write, sigset_t *old_set)
344 TranslationBlock *tb;
348 #if defined(DEBUG_SIGNAL)
349 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
350 pc, address, is_write, *(unsigned long *)old_set);
352 /* XXX: locking issue */
353 if (is_write && page_unprotect(address)) {
358 /* the PC is inside the translated code. It means that we have
359 a virtual CPU fault */
360 ret = cpu_x86_search_pc(tb, &found_pc, pc);
363 env->eip = found_pc - tb->cs_base;
365 /* we restore the process signal mask as the sigreturn should
366 do it (XXX: use sigsetjmp) */
367 sigprocmask(SIG_SETMASK, old_set, NULL);
368 raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
369 /* never comes here */
376 #if defined(__i386__)
378 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
381 struct ucontext *uc = puc;
388 #define REG_TRAPNO TRAPNO
390 pc = uc->uc_mcontext.gregs[REG_EIP];
391 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
392 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
393 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
397 #elif defined(__powerpc)
399 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
402 struct ucontext *uc = puc;
403 struct pt_regs *regs = uc->uc_mcontext.regs;
411 if (regs->dsisr & 0x00800000)
414 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
417 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
418 is_write, &uc->uc_sigmask);
421 #elif defined(__alpha__)
423 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
426 struct ucontext *uc = puc;
427 uint32_t *pc = uc->uc_mcontext.sc_pc;
431 /* XXX: need kernel patch to get write flag faster */
432 switch (insn >> 26) {
447 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
448 is_write, &uc->uc_sigmask);
450 #elif defined(__sparc__)
452 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
455 uint32_t *regs = (uint32_t *)(info + 1);
456 void *sigmask = (regs + 20);
461 /* XXX: is there a standard glibc define ? */
463 /* XXX: need kernel patch to get write flag faster */
465 insn = *(uint32_t *)pc;
466 if ((insn >> 30) == 3) {
467 switch((insn >> 19) & 0x3f) {
479 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
483 #elif defined(__arm__)
485 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
488 struct ucontext *uc = puc;
492 pc = uc->uc_mcontext.gregs[R15];
493 /* XXX: compute is_write */
495 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
502 #error CPU specific signal handler needed