2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include "exec-i386.h"
24 //#define DEBUG_SIGNAL
26 /* main execution loop */
30 spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
34 spin_lock(&global_cpu_lock);
39 spin_unlock(&global_cpu_lock);
42 /* exception support */
43 /* NOTE: not static to force relocation generation by GCC */
44 void raise_exception_err(int exception_index, int error_code)
46 /* NOTE: the register at this point must be saved by hand because
47 longjmp restore them */
49 /* We have to stay in the same register window as our caller,
52 __asm__ __volatile__("restore\n\t"
56 env->regs[R_EAX] = EAX;
59 env->regs[R_ECX] = ECX;
62 env->regs[R_EDX] = EDX;
65 env->regs[R_EBX] = EBX;
68 env->regs[R_ESP] = ESP;
71 env->regs[R_EBP] = EBP;
74 env->regs[R_ESI] = ESI;
77 env->regs[R_EDI] = EDI;
79 env->exception_index = exception_index;
80 env->error_code = error_code;
81 longjmp(env->jmp_env, 1);
84 /* short cut if error_code is 0 or not present */
85 void raise_exception(int exception_index)
87 raise_exception_err(exception_index, 0);
90 int cpu_x86_exec(CPUX86State *env1)
92 int saved_T0, saved_T1, saved_A0;
93 CPUX86State *saved_env;
118 int code_gen_size, ret, code_size;
119 void (*gen_func)(void);
120 TranslationBlock *tb, **ptb;
121 uint8_t *tc_ptr, *cs_base, *pc;
124 /* first we save global registers */
132 EAX = env->regs[R_EAX];
136 ECX = env->regs[R_ECX];
140 EDX = env->regs[R_EDX];
144 EBX = env->regs[R_EBX];
148 ESP = env->regs[R_ESP];
152 EBP = env->regs[R_EBP];
156 ESI = env->regs[R_ESI];
160 EDI = env->regs[R_EDI];
163 /* put eflags in CPU temporary format */
164 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
165 DF = 1 - (2 * ((env->eflags >> 10) & 1));
166 CC_OP = CC_OP_EFLAGS;
167 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
168 env->interrupt_request = 0;
170 /* prepare setjmp context for exception handling */
171 if (setjmp(env->jmp_env) == 0) {
172 T0 = 0; /* force lookup of first TB */
174 if (env->interrupt_request) {
175 raise_exception(EXCP_INTERRUPT);
179 /* XXX: save all volatile state in cpu state */
180 /* restore flags in standard format */
181 env->regs[R_EAX] = EAX;
182 env->regs[R_EBX] = EBX;
183 env->regs[R_ECX] = ECX;
184 env->regs[R_EDX] = EDX;
185 env->regs[R_ESI] = ESI;
186 env->regs[R_EDI] = EDI;
187 env->regs[R_EBP] = EBP;
188 env->regs[R_ESP] = ESP;
189 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
190 cpu_x86_dump_state(env, logfile, 0);
191 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
194 /* we compute the CPU state. We assume it will not
195 change during the whole generated block. */
196 flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
197 flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
198 flags |= (((unsigned long)env->seg_cache[R_DS].base |
199 (unsigned long)env->seg_cache[R_ES].base |
200 (unsigned long)env->seg_cache[R_SS].base) != 0) <<
201 GEN_FLAG_ADDSEG_SHIFT;
202 if (!(env->eflags & VM_MASK)) {
203 flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
205 /* NOTE: a dummy CPL is kept */
206 flags |= (1 << GEN_FLAG_VM_SHIFT);
207 flags |= (3 << GEN_FLAG_CPL_SHIFT);
209 flags |= (env->eflags & (IOPL_MASK | TF_MASK));
210 cs_base = env->seg_cache[R_CS].base;
211 pc = cs_base + env->eip;
212 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
216 /* if no translated code available, then translate it now */
217 tb = tb_alloc((unsigned long)pc);
219 /* flush must be done */
221 /* cannot fail at this point */
222 tb = tb_alloc((unsigned long)pc);
223 /* don't forget to invalidate previous TB info */
224 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
227 tc_ptr = code_gen_ptr;
229 ret = cpu_x86_gen_code(code_gen_ptr, CODE_GEN_MAX_SIZE,
230 &code_gen_size, pc, cs_base, flags,
232 /* if invalid instruction, signal it */
234 /* NOTE: the tb is allocated but not linked, so we
236 spin_unlock(&tb_lock);
237 raise_exception(EXCP06_ILLOP);
240 tb->size = code_size;
241 tb->cs_base = (unsigned long)cs_base;
243 tb->hash_next = NULL;
245 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
246 spin_unlock(&tb_lock);
250 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
251 (long)tb->tc_ptr, (long)tb->pc,
252 lookup_symbol((void *)tb->pc));
255 /* see if we can patch the calling TB */
256 if (T0 != 0 && !(env->eflags & TF_MASK)) {
258 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
259 spin_unlock(&tb_lock);
264 /* execute the generated code */
265 gen_func = (void *)tc_ptr;
267 __asm__ __volatile__("call %0\n\t"
271 : "i0", "i1", "i2", "i3", "i4", "i5");
277 ret = env->exception_index;
279 /* restore flags in standard format */
280 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
282 /* restore global registers */
314 void cpu_x86_interrupt(CPUX86State *s)
316 s->interrupt_request = 1;
320 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
322 CPUX86State *saved_env;
326 load_seg(seg_reg, selector);
340 #include <sys/ucontext.h>
342 /* 'pc' is the host PC at which the exception was raised. 'address' is
343 the effective address of the memory exception. 'is_write' is 1 if a
344 write caused the exception and otherwise 0'. 'old_set' is the
345 signal set which should be restored */
346 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
347 int is_write, sigset_t *old_set)
349 #if defined(DEBUG_SIGNAL)
350 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
351 pc, address, is_write, *(unsigned long *)old_set);
353 /* XXX: locking issue */
354 if (is_write && page_unprotect(address)) {
357 if (pc >= (unsigned long)code_gen_buffer &&
358 pc < (unsigned long)code_gen_buffer + CODE_GEN_BUFFER_SIZE) {
359 /* the PC is inside the translated code. It means that we have
360 a virtual CPU fault */
361 /* we restore the process signal mask as the sigreturn should
363 sigprocmask(SIG_SETMASK, old_set, NULL);
364 /* XXX: need to compute virtual pc position by retranslating
365 code. The rest of the CPU state should be correct. */
367 raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
368 /* never comes here */
375 #if defined(__i386__)
377 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
380 struct ucontext *uc = puc;
387 #define REG_TRAPNO TRAPNO
389 pc = uc->uc_mcontext.gregs[REG_EIP];
390 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
391 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
392 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
396 #elif defined(__powerpc)
398 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
401 struct ucontext *uc = puc;
402 struct pt_regs *regs = uc->uc_mcontext.regs;
410 if (regs->dsisr & 0x00800000)
413 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
416 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
417 is_write, &uc->uc_sigmask);
422 #error CPU specific signal handler needed