36 #define TRAP_FLAG 0x0100
37 #define INTERRUPT_FLAG 0x0200
38 #define DIRECTION_FLAG 0x0400
39 #define IOPL_FLAG_MASK 0x3000
40 #define NESTED_FLAG 0x4000
41 #define BYTE_FL 0x8000 /* Intel reserved! */
42 #define RF_FLAG 0x10000
43 #define VM_FLAG 0x20000
47 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
48 CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
49 CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
51 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
55 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
59 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
63 CC_OP_INCB, /* modify all flags except, CC_DST = res */
67 CC_OP_DECB, /* modify all flags except, CC_DST = res */
71 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
78 typedef struct CPU86State {
79 /* standard registers */
81 uint32_t pc; /* cs_case + eip value */
88 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
91 uint8_t *segs_base[6];
94 /* emulator internal variables */
95 uint32_t t0; /* temporary t0 storage */
96 uint32_t t1; /* temporary t1 storage */
97 uint32_t a0; /* temporary a0 storage (address) */
100 static inline int ldub(void *ptr)
102 return *(uint8_t *)ptr;
105 static inline int ldsb(void *ptr)
107 return *(int8_t *)ptr;
110 static inline int lduw(void *ptr)
112 return *(uint16_t *)ptr;
115 static inline int ldsw(void *ptr)
117 return *(int16_t *)ptr;
120 static inline int ldl(void *ptr)
122 return *(uint32_t *)ptr;
126 static inline void stb(void *ptr, int v)
131 static inline void stw(void *ptr, int v)
133 *(uint16_t *)ptr = v;
136 static inline void stl(void *ptr, int v)
138 *(uint32_t *)ptr = v;
141 void port_outb(int addr, int val);
142 void port_outw(int addr, int val);
143 void port_outl(int addr, int val);
144 int port_inb(int addr);
145 int port_inw(int addr);
146 int port_inl(int addr);
148 #endif /* CPU_I386_H */