2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
51 /* segment descriptor fields */
52 #define DESC_G_MASK (1 << 23)
53 #define DESC_B_MASK (1 << 22)
54 #define DESC_AVL_MASK (1 << 20)
55 #define DESC_P_MASK (1 << 15)
56 #define DESC_DPL_SHIFT 13
57 #define DESC_S_MASK (1 << 12)
58 #define DESC_TYPE_SHIFT 8
59 #define DESC_A_MASK (1 << 8)
61 #define DESC_CS_MASK (1 << 11)
62 #define DESC_C_MASK (1 << 10)
63 #define DESC_R_MASK (1 << 9)
65 #define DESC_E_MASK (1 << 10)
66 #define DESC_W_MASK (1 << 9)
76 #define TF_MASK 0x00000100
77 #define IF_MASK 0x00000200
78 #define DF_MASK 0x00000400
79 #define IOPL_MASK 0x00003000
80 #define NT_MASK 0x00004000
81 #define RF_MASK 0x00010000
82 #define VM_MASK 0x00020000
83 #define AC_MASK 0x00040000
84 #define VIF_MASK 0x00080000
85 #define VIP_MASK 0x00100000
86 #define ID_MASK 0x00200000
88 #define CR0_PE_MASK (1 << 0)
89 #define CR0_TS_MASK (1 << 3)
90 #define CR0_WP_MASK (1 << 16)
91 #define CR0_AM_MASK (1 << 18)
92 #define CR0_PG_MASK (1 << 31)
94 #define CR4_VME_MASK (1 << 0)
95 #define CR4_PVI_MASK (1 << 1)
96 #define CR4_TSD_MASK (1 << 2)
97 #define CR4_DE_MASK (1 << 3)
100 #define EXCP01_SSTP 1
102 #define EXCP03_INT3 3
103 #define EXCP04_INTO 4
104 #define EXCP05_BOUND 5
105 #define EXCP06_ILLOP 6
106 #define EXCP07_PREX 7
107 #define EXCP08_DBLE 8
108 #define EXCP09_XERR 9
109 #define EXCP0A_TSS 10
110 #define EXCP0B_NOSEG 11
111 #define EXCP0C_STACK 12
112 #define EXCP0D_GPF 13
113 #define EXCP0E_PAGE 14
114 #define EXCP10_COPR 16
115 #define EXCP11_ALGN 17
116 #define EXCP12_MCHK 18
118 #define EXCP_INTERRUPT 256 /* async interruption */
121 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
122 CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
123 CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
125 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
129 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
133 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
137 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
141 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
145 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
149 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
153 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
157 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
165 #define USE_X86LDOUBLE
168 #ifdef USE_X86LDOUBLE
169 typedef long double CPU86_LDouble;
171 typedef double CPU86_LDouble;
174 typedef struct SegmentCache {
181 typedef struct CPUX86State {
182 /* standard registers */
185 uint32_t eflags; /* eflags register. During CPU emulation, CC
186 flags and DF are set to zero because they are
189 /* emulator internal eflags handling */
193 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
196 unsigned int fpstt; /* top of stack index */
199 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
200 CPU86_LDouble fpregs[8];
202 /* emulator internal variables */
212 SegmentCache segs[6]; /* selector values */
215 SegmentCache gdt; /* only base and limit are used */
216 SegmentCache idt; /* only base and limit are used */
218 /* exception/interrupt handling */
222 uint32_t cr[5]; /* NOTE: cr1 is unused */
223 uint32_t dr[8]; /* debug registers */
224 int interrupt_request;
231 void cpu_x86_outb(CPUX86State *env, int addr, int val);
232 void cpu_x86_outw(CPUX86State *env, int addr, int val);
233 void cpu_x86_outl(CPUX86State *env, int addr, int val);
234 int cpu_x86_inb(CPUX86State *env, int addr);
235 int cpu_x86_inw(CPUX86State *env, int addr);
236 int cpu_x86_inl(CPUX86State *env, int addr);
239 CPUX86State *cpu_x86_init(void);
240 int cpu_x86_exec(CPUX86State *s);
241 void cpu_x86_interrupt(CPUX86State *s);
242 void cpu_x86_close(CPUX86State *s);
244 /* needed to load some predefinied segment registers */
245 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
247 /* simulate fsave/frstor */
248 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
249 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
251 /* you can call this signal handler from your SIGBUS and SIGSEGV
252 signal handlers to inform the virtual CPU of exceptions. non zero
253 is returned if the signal was handled by the virtual CPU. */
255 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
259 #define X86_DUMP_FPU 0x0001 /* dump FPU state too */
260 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
261 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
263 #define TARGET_PAGE_BITS 12
266 #endif /* CPU_I386_H */