2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
50 /* segment descriptor fields */
51 #define DESC_G_MASK (1 << 23)
52 #define DESC_B_SHIFT 22
53 #define DESC_B_MASK (1 << DESC_B_SHIFT)
54 #define DESC_AVL_MASK (1 << 20)
55 #define DESC_P_MASK (1 << 15)
56 #define DESC_DPL_SHIFT 13
57 #define DESC_S_MASK (1 << 12)
58 #define DESC_TYPE_SHIFT 8
59 #define DESC_A_MASK (1 << 8)
61 #define DESC_CS_MASK (1 << 11)
62 #define DESC_C_MASK (1 << 10)
63 #define DESC_R_MASK (1 << 9)
65 #define DESC_E_MASK (1 << 10)
66 #define DESC_W_MASK (1 << 9)
76 #define TF_MASK 0x00000100
77 #define IF_MASK 0x00000200
78 #define DF_MASK 0x00000400
79 #define IOPL_MASK 0x00003000
80 #define NT_MASK 0x00004000
81 #define RF_MASK 0x00010000
82 #define VM_MASK 0x00020000
83 #define AC_MASK 0x00040000
84 #define VIF_MASK 0x00080000
85 #define VIP_MASK 0x00100000
86 #define ID_MASK 0x00200000
88 #define CR0_PE_MASK (1 << 0)
89 #define CR0_TS_MASK (1 << 3)
90 #define CR0_WP_MASK (1 << 16)
91 #define CR0_AM_MASK (1 << 18)
92 #define CR0_PG_MASK (1 << 31)
94 #define CR4_VME_MASK (1 << 0)
95 #define CR4_PVI_MASK (1 << 1)
96 #define CR4_TSD_MASK (1 << 2)
97 #define CR4_DE_MASK (1 << 3)
98 #define CR4_PSE_MASK (1 << 4)
100 #define PG_PRESENT_BIT 0
102 #define PG_USER_BIT 2
105 #define PG_ACCESSED_BIT 5
106 #define PG_DIRTY_BIT 6
108 #define PG_GLOBAL_BIT 8
110 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
111 #define PG_RW_MASK (1 << PG_RW_BIT)
112 #define PG_USER_MASK (1 << PG_USER_BIT)
113 #define PG_PWT_MASK (1 << PG_PWT_BIT)
114 #define PG_PCD_MASK (1 << PG_PCD_BIT)
115 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
116 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
117 #define PG_PSE_MASK (1 << PG_PSE_BIT)
118 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
120 #define PG_ERROR_W_BIT 1
122 #define PG_ERROR_P_MASK 0x01
123 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
124 #define PG_ERROR_U_MASK 0x04
125 #define PG_ERROR_RSVD_MASK 0x08
127 #define MSR_IA32_APICBASE 0x1b
128 #define MSR_IA32_APICBASE_BSP (1<<8)
129 #define MSR_IA32_APICBASE_ENABLE (1<<11)
130 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
132 #define MSR_IA32_SYSENTER_CS 0x174
133 #define MSR_IA32_SYSENTER_ESP 0x175
134 #define MSR_IA32_SYSENTER_EIP 0x176
136 #define EXCP00_DIVZ 0
137 #define EXCP01_SSTP 1
139 #define EXCP03_INT3 3
140 #define EXCP04_INTO 4
141 #define EXCP05_BOUND 5
142 #define EXCP06_ILLOP 6
143 #define EXCP07_PREX 7
144 #define EXCP08_DBLE 8
145 #define EXCP09_XERR 9
146 #define EXCP0A_TSS 10
147 #define EXCP0B_NOSEG 11
148 #define EXCP0C_STACK 12
149 #define EXCP0D_GPF 13
150 #define EXCP0E_PAGE 14
151 #define EXCP10_COPR 16
152 #define EXCP11_ALGN 17
153 #define EXCP12_MCHK 18
156 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
157 CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
158 CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
160 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
164 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
168 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
172 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
176 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
180 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
184 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
188 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
192 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
200 #define USE_X86LDOUBLE
203 #ifdef USE_X86LDOUBLE
204 typedef long double CPU86_LDouble;
206 typedef double CPU86_LDouble;
209 typedef struct SegmentCache {
216 typedef struct CPUX86State {
217 /* standard registers */
220 uint32_t eflags; /* eflags register. During CPU emulation, CC
221 flags and DF are set to zero because they are
224 /* emulator internal eflags handling */
228 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
231 unsigned int fpstt; /* top of stack index */
234 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
235 CPU86_LDouble fpregs[8];
237 /* emulator internal variables */
247 SegmentCache segs[6]; /* selector values */
250 SegmentCache gdt; /* only base and limit are used */
251 SegmentCache idt; /* only base and limit are used */
252 int cpl; /* current cpl */
253 int soft_mmu; /* TRUE if soft mmu is being used */
255 /* sysenter registers */
256 uint32_t sysenter_cs;
257 uint32_t sysenter_esp;
258 uint32_t sysenter_eip;
260 /* exception/interrupt handling */
264 int exception_is_int;
265 int exception_next_eip;
266 struct TranslationBlock *current_tb; /* currently executing TB */
267 uint32_t cr[5]; /* NOTE: cr1 is unused */
268 uint32_t dr[8]; /* debug registers */
269 int interrupt_request;
270 int user_mode_only; /* user mode only simulation */
272 /* soft mmu support */
273 /* 0 = kernel, 1 = user */
274 CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
275 CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
277 /* ice debug support */
278 uint32_t breakpoints[MAX_BREAKPOINTS];
280 int singlestep_enabled;
287 void cpu_x86_outb(CPUX86State *env, int addr, int val);
288 void cpu_x86_outw(CPUX86State *env, int addr, int val);
289 void cpu_x86_outl(CPUX86State *env, int addr, int val);
290 int cpu_x86_inb(CPUX86State *env, int addr);
291 int cpu_x86_inw(CPUX86State *env, int addr);
292 int cpu_x86_inl(CPUX86State *env, int addr);
295 CPUX86State *cpu_x86_init(void);
296 int cpu_x86_exec(CPUX86State *s);
297 void cpu_x86_close(CPUX86State *s);
298 int cpu_x86_get_pic_interrupt(CPUX86State *s);
300 /* needed to load some predefinied segment registers */
301 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
303 /* wrapper, just in case memory mappings must be changed */
304 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
309 /* simulate fsave/frstor */
310 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
311 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
313 /* you can call this signal handler from your SIGBUS and SIGSEGV
314 signal handlers to inform the virtual CPU of exceptions. non zero
315 is returned if the signal was handled by the virtual CPU. */
317 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
321 void cpu_x86_init_mmu(CPUX86State *env);
322 extern int phys_ram_size;
323 extern int phys_ram_fd;
324 extern uint8_t *phys_ram_base;
327 #define X86_DUMP_FPU 0x0001 /* dump FPU state too */
328 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
329 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
331 #define TARGET_PAGE_BITS 12
334 #endif /* CPU_I386_H */