2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include "exec-i386.h"
31 //#define DEBUG_SIGNAL
33 #if defined(TARGET_ARM)
34 /* XXX: unify with i386 target */
35 void cpu_loop_exit(void)
37 longjmp(env->jmp_env, 1);
41 /* main execution loop */
43 int cpu_exec(CPUState *env1)
45 int saved_T0, saved_T1, saved_T2;
74 int code_gen_size, ret, interrupt_request;
75 void (*gen_func)(void);
76 TranslationBlock *tb, **ptb;
77 uint8_t *tc_ptr, *cs_base, *pc;
80 /* first we save global registers */
87 /* we also save i7 because longjmp may not restore it */
88 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
91 #if defined(TARGET_I386)
94 EAX = env->regs[R_EAX];
98 ECX = env->regs[R_ECX];
102 EDX = env->regs[R_EDX];
106 EBX = env->regs[R_EBX];
110 ESP = env->regs[R_ESP];
114 EBP = env->regs[R_EBP];
118 ESI = env->regs[R_ESI];
122 EDI = env->regs[R_EDI];
125 /* put eflags in CPU temporary format */
126 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
127 DF = 1 - (2 * ((env->eflags >> 10) & 1));
128 CC_OP = CC_OP_EFLAGS;
129 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
130 #elif defined(TARGET_ARM)
134 env->CF = (psr >> 29) & 1;
135 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
136 env->VF = (psr << 3) & 0x80000000;
137 env->cpsr = psr & ~0xf0000000;
140 #error unsupported target CPU
142 env->exception_index = -1;
144 /* prepare setjmp context for exception handling */
146 if (setjmp(env->jmp_env) == 0) {
147 /* if an exception is pending, we execute it here */
148 if (env->exception_index >= 0) {
149 if (env->exception_index >= EXCP_INTERRUPT) {
150 /* exit request from the cpu execution loop */
151 ret = env->exception_index;
153 } else if (env->user_mode_only) {
154 /* if user mode only, we simulate a fake exception
155 which will be hanlded outside the cpu execution
157 #if defined(TARGET_I386)
158 do_interrupt_user(env->exception_index,
159 env->exception_is_int,
161 env->exception_next_eip);
163 ret = env->exception_index;
166 #if defined(TARGET_I386)
167 /* simulate a real cpu exception. On i386, it can
168 trigger new exceptions, but we do not handle
169 double or triple faults yet. */
170 do_interrupt(env->exception_index,
171 env->exception_is_int,
173 env->exception_next_eip);
176 env->exception_index = -1;
178 T0 = 0; /* force lookup of first TB */
181 /* g1 can be modified by some libc? functions */
184 interrupt_request = env->interrupt_request;
185 if (interrupt_request) {
186 #if defined(TARGET_I386)
187 /* if hardware interrupt pending, we execute it */
188 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
189 (env->eflags & IF_MASK)) {
191 intno = cpu_x86_get_pic_interrupt(env);
193 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
195 do_interrupt(intno, 0, 0, 0);
196 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
197 /* ensure that no TB jump will be modified as
198 the program flow was changed */
206 if (interrupt_request & CPU_INTERRUPT_EXIT) {
207 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
208 env->exception_index = EXCP_INTERRUPT;
214 #if defined(TARGET_I386)
215 /* restore flags in standard format */
216 env->regs[R_EAX] = EAX;
217 env->regs[R_EBX] = EBX;
218 env->regs[R_ECX] = ECX;
219 env->regs[R_EDX] = EDX;
220 env->regs[R_ESI] = ESI;
221 env->regs[R_EDI] = EDI;
222 env->regs[R_EBP] = EBP;
223 env->regs[R_ESP] = ESP;
224 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
225 cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
226 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
227 #elif defined(TARGET_ARM)
228 env->cpsr = compute_cpsr();
229 cpu_arm_dump_state(env, logfile, 0);
230 env->cpsr &= ~0xf0000000;
232 #error unsupported target CPU
236 /* we compute the CPU state. We assume it will not
237 change during the whole generated block. */
238 #if defined(TARGET_I386)
239 flags = (env->segs[R_CS].flags & DESC_B_MASK)
240 >> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
241 flags |= (env->segs[R_SS].flags & DESC_B_MASK)
242 >> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
243 flags |= (((unsigned long)env->segs[R_DS].base |
244 (unsigned long)env->segs[R_ES].base |
245 (unsigned long)env->segs[R_SS].base) != 0) <<
246 GEN_FLAG_ADDSEG_SHIFT;
247 flags |= env->cpl << GEN_FLAG_CPL_SHIFT;
248 flags |= env->soft_mmu << GEN_FLAG_SOFT_MMU_SHIFT;
249 flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT);
250 flags |= (env->eflags & (IOPL_MASK | TF_MASK));
251 cs_base = env->segs[R_CS].base;
252 pc = cs_base + env->eip;
253 #elif defined(TARGET_ARM)
256 pc = (uint8_t *)env->regs[15];
258 #error unsupported CPU
260 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
264 /* if no translated code available, then translate it now */
265 tb = tb_alloc((unsigned long)pc);
267 /* flush must be done */
269 /* cannot fail at this point */
270 tb = tb_alloc((unsigned long)pc);
271 /* don't forget to invalidate previous TB info */
272 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
275 tc_ptr = code_gen_ptr;
277 tb->cs_base = (unsigned long)cs_base;
279 ret = cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
280 #if defined(TARGET_I386)
281 /* XXX: suppress that, this is incorrect */
282 /* if invalid instruction, signal it */
284 /* NOTE: the tb is allocated but not linked, so we
286 spin_unlock(&tb_lock);
287 raise_exception(EXCP06_ILLOP);
291 tb->hash_next = NULL;
293 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
294 spin_unlock(&tb_lock);
298 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
299 (long)tb->tc_ptr, (long)tb->pc,
300 lookup_symbol((void *)tb->pc));
306 /* see if we can patch the calling TB. XXX: remove TF test */
308 #if defined(TARGET_I386)
309 && !(env->eflags & TF_MASK)
313 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
314 spin_unlock(&tb_lock);
317 env->current_tb = tb;
318 /* execute the generated code */
319 gen_func = (void *)tc_ptr;
320 #if defined(__sparc__)
321 __asm__ __volatile__("call %0\n\t"
325 : "i0", "i1", "i2", "i3", "i4", "i5");
326 #elif defined(__arm__)
327 asm volatile ("mov pc, %0\n\t"
328 ".global exec_loop\n\t"
332 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
336 env->current_tb = NULL;
337 /* reset soft MMU for next block (it can currently
338 only be set by a memory fault) */
339 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
342 /* do not allow linking to another block */
352 #if defined(TARGET_I386)
353 /* restore flags in standard format */
354 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
356 /* restore global registers */
381 #elif defined(TARGET_ARM)
382 env->cpsr = compute_cpsr();
384 #error unsupported target CPU
387 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
396 #if defined(TARGET_I386)
398 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
400 CPUX86State *saved_env;
404 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
407 sc = &env->segs[seg_reg];
408 sc->base = (void *)(selector << 4);
411 sc->selector = selector;
413 load_seg(seg_reg, selector, 0);
418 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
420 CPUX86State *saved_env;
425 helper_fsave(ptr, data32);
430 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
432 CPUX86State *saved_env;
437 helper_frstor(ptr, data32);
442 #endif /* TARGET_I386 */
454 #include <sys/ucontext.h>
456 #if defined(TARGET_I386)
458 /* 'pc' is the host PC at which the exception was raised. 'address' is
459 the effective address of the memory exception. 'is_write' is 1 if a
460 write caused the exception and otherwise 0'. 'old_set' is the
461 signal set which should be restored */
462 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
463 int is_write, sigset_t *old_set)
465 TranslationBlock *tb;
469 env = cpu_single_env; /* XXX: find a correct solution for multithread */
470 #if defined(DEBUG_SIGNAL)
471 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
472 pc, address, is_write, *(unsigned long *)old_set);
474 /* XXX: locking issue */
475 if (is_write && page_unprotect(address)) {
478 /* see if it is an MMU fault */
479 ret = cpu_x86_handle_mmu_fault(env, address, is_write);
481 return 0; /* not an MMU fault */
483 return 1; /* the MMU fault was handled without causing real CPU fault */
484 /* now we have a real cpu fault */
487 /* the PC is inside the translated code. It means that we have
488 a virtual CPU fault */
489 cpu_restore_state(tb, env, pc);
493 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
494 env->eip, env->cr[2], env->error_code);
496 /* we restore the process signal mask as the sigreturn should
497 do it (XXX: use sigsetjmp) */
498 sigprocmask(SIG_SETMASK, old_set, NULL);
499 raise_exception_err(EXCP0E_PAGE, env->error_code);
501 /* activate soft MMU for this block */
503 sigprocmask(SIG_SETMASK, old_set, NULL);
506 /* never comes here */
510 #elif defined(TARGET_ARM)
511 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
512 int is_write, sigset_t *old_set)
518 #error unsupported target CPU
521 #if defined(__i386__)
523 int cpu_signal_handler(int host_signum, struct siginfo *info,
526 struct ucontext *uc = puc;
533 #define REG_TRAPNO TRAPNO
535 pc = uc->uc_mcontext.gregs[REG_EIP];
536 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
537 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
538 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
542 #elif defined(__powerpc)
544 int cpu_signal_handler(int host_signum, struct siginfo *info,
547 struct ucontext *uc = puc;
548 struct pt_regs *regs = uc->uc_mcontext.regs;
556 if (regs->dsisr & 0x00800000)
559 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
562 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
563 is_write, &uc->uc_sigmask);
566 #elif defined(__alpha__)
568 int cpu_signal_handler(int host_signum, struct siginfo *info,
571 struct ucontext *uc = puc;
572 uint32_t *pc = uc->uc_mcontext.sc_pc;
576 /* XXX: need kernel patch to get write flag faster */
577 switch (insn >> 26) {
592 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
593 is_write, &uc->uc_sigmask);
595 #elif defined(__sparc__)
597 int cpu_signal_handler(int host_signum, struct siginfo *info,
600 uint32_t *regs = (uint32_t *)(info + 1);
601 void *sigmask = (regs + 20);
606 /* XXX: is there a standard glibc define ? */
608 /* XXX: need kernel patch to get write flag faster */
610 insn = *(uint32_t *)pc;
611 if ((insn >> 30) == 3) {
612 switch((insn >> 19) & 0x3f) {
624 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
628 #elif defined(__arm__)
630 int cpu_signal_handler(int host_signum, struct siginfo *info,
633 struct ucontext *uc = puc;
637 pc = uc->uc_mcontext.gregs[R15];
638 /* XXX: compute is_write */
640 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
645 #elif defined(__mc68000)
647 int cpu_signal_handler(int host_signum, struct siginfo *info,
650 struct ucontext *uc = puc;
654 pc = uc->uc_mcontext.gregs[16];
655 /* XXX: compute is_write */
657 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
664 #error host CPU specific signal handler needed