2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 int tb_invalidated_flag;
27 //#define DEBUG_SIGNAL
29 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
30 /* XXX: unify with i386 target */
31 void cpu_loop_exit(void)
33 longjmp(env->jmp_env, 1);
37 /* main execution loop */
39 int cpu_exec(CPUState *env1)
41 int saved_T0, saved_T1, saved_T2;
70 int code_gen_size, ret, interrupt_request;
71 void (*gen_func)(void);
72 TranslationBlock *tb, **ptb;
73 uint8_t *tc_ptr, *cs_base, *pc;
76 /* first we save global registers */
83 /* we also save i7 because longjmp may not restore it */
84 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
87 #if defined(TARGET_I386)
90 EAX = env->regs[R_EAX];
94 ECX = env->regs[R_ECX];
98 EDX = env->regs[R_EDX];
102 EBX = env->regs[R_EBX];
106 ESP = env->regs[R_ESP];
110 EBP = env->regs[R_EBP];
114 ESI = env->regs[R_ESI];
118 EDI = env->regs[R_EDI];
121 /* put eflags in CPU temporary format */
122 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
123 DF = 1 - (2 * ((env->eflags >> 10) & 1));
124 CC_OP = CC_OP_EFLAGS;
125 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
126 #elif defined(TARGET_ARM)
130 env->CF = (psr >> 29) & 1;
131 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
132 env->VF = (psr << 3) & 0x80000000;
133 env->cpsr = psr & ~0xf0000000;
135 #elif defined(TARGET_SPARC)
136 #elif defined(TARGET_PPC)
138 #error unsupported target CPU
140 env->exception_index = -1;
142 /* prepare setjmp context for exception handling */
144 if (setjmp(env->jmp_env) == 0) {
145 /* if an exception is pending, we execute it here */
146 if (env->exception_index >= 0) {
147 if (env->exception_index >= EXCP_INTERRUPT) {
148 /* exit request from the cpu execution loop */
149 ret = env->exception_index;
151 } else if (env->user_mode_only) {
152 /* if user mode only, we simulate a fake exception
153 which will be hanlded outside the cpu execution
155 #if defined(TARGET_I386)
156 do_interrupt_user(env->exception_index,
157 env->exception_is_int,
159 env->exception_next_eip);
161 ret = env->exception_index;
164 #if defined(TARGET_I386)
165 /* simulate a real cpu exception. On i386, it can
166 trigger new exceptions, but we do not handle
167 double or triple faults yet. */
168 do_interrupt(env->exception_index,
169 env->exception_is_int,
171 env->exception_next_eip, 0);
172 #elif defined(TARGET_PPC)
176 env->exception_index = -1;
178 T0 = 0; /* force lookup of first TB */
181 /* g1 can be modified by some libc? functions */
184 interrupt_request = env->interrupt_request;
185 if (__builtin_expect(interrupt_request, 0)) {
186 #if defined(TARGET_I386)
187 /* if hardware interrupt pending, we execute it */
188 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
189 (env->eflags & IF_MASK) &&
190 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
192 intno = cpu_x86_get_pic_interrupt(env);
194 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
196 do_interrupt(intno, 0, 0, 0, 1);
197 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
198 /* ensure that no TB jump will be modified as
199 the program flow was changed */
206 #elif defined(TARGET_PPC)
207 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
208 do_queue_exception(EXCP_EXTERNAL);
209 if (check_exception_state(env))
211 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
214 if (interrupt_request & CPU_INTERRUPT_EXIT) {
215 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
216 env->exception_index = EXCP_INTERRUPT;
222 #if defined(TARGET_I386)
223 /* restore flags in standard format */
224 env->regs[R_EAX] = EAX;
225 env->regs[R_EBX] = EBX;
226 env->regs[R_ECX] = ECX;
227 env->regs[R_EDX] = EDX;
228 env->regs[R_ESI] = ESI;
229 env->regs[R_EDI] = EDI;
230 env->regs[R_EBP] = EBP;
231 env->regs[R_ESP] = ESP;
232 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
233 cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
234 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
235 #elif defined(TARGET_ARM)
236 env->cpsr = compute_cpsr();
237 cpu_arm_dump_state(env, logfile, 0);
238 env->cpsr &= ~0xf0000000;
239 #elif defined(TARGET_SPARC)
240 cpu_sparc_dump_state (env, logfile, 0);
241 #elif defined(TARGET_PPC)
242 cpu_ppc_dump_state(env, logfile, 0);
244 #error unsupported target CPU
248 /* we record a subset of the CPU state. It will
249 always be the same before a given translated block
251 #if defined(TARGET_I386)
253 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
254 cs_base = env->segs[R_CS].base;
255 pc = cs_base + env->eip;
256 #elif defined(TARGET_ARM)
259 pc = (uint8_t *)env->regs[15];
260 #elif defined(TARGET_SPARC)
262 cs_base = (uint8_t *)env->npc;
263 pc = (uint8_t *) env->pc;
264 #elif defined(TARGET_PPC)
267 pc = (uint8_t *)env->nip;
269 #error unsupported CPU
271 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
274 TranslationBlock **ptb1;
276 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
281 tb_invalidated_flag = 0;
283 /* find translated block using physical mappings */
284 phys_pc = get_phys_addr_code(env, (unsigned long)pc);
285 phys_page1 = phys_pc & TARGET_PAGE_MASK;
287 h = tb_phys_hash_func(phys_pc);
288 ptb1 = &tb_phys_hash[h];
293 if (tb->pc == (unsigned long)pc &&
294 tb->page_addr[0] == phys_page1 &&
295 tb->cs_base == (unsigned long)cs_base &&
296 tb->flags == flags) {
297 /* check next page if needed */
298 if (tb->page_addr[1] != -1) {
299 virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) +
301 phys_page2 = get_phys_addr_code(env, virt_page2);
302 if (tb->page_addr[1] == phys_page2)
308 ptb1 = &tb->phys_hash_next;
311 /* if no translated code available, then translate it now */
312 tb = tb_alloc((unsigned long)pc);
314 /* flush must be done */
316 /* cannot fail at this point */
317 tb = tb_alloc((unsigned long)pc);
318 /* don't forget to invalidate previous TB info */
319 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
322 tc_ptr = code_gen_ptr;
324 tb->cs_base = (unsigned long)cs_base;
326 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
327 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
329 /* check next page if needed */
330 virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK;
332 if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) {
333 phys_page2 = get_phys_addr_code(env, virt_page2);
335 tb_link_phys(tb, phys_pc, phys_page2);
338 if (tb_invalidated_flag) {
339 /* as some TB could have been invalidated because
340 of memory exceptions while generating the code, we
341 must recompute the hash index here */
342 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
344 ptb = &(*ptb)->hash_next;
347 /* we add the TB in the virtual pc hash table */
349 tb->hash_next = NULL;
351 spin_unlock(&tb_lock);
355 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
356 (long)tb->tc_ptr, (long)tb->pc,
357 lookup_symbol((void *)tb->pc));
363 /* see if we can patch the calling TB. */
366 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
367 spin_unlock(&tb_lock);
370 env->current_tb = tb;
371 /* execute the generated code */
372 gen_func = (void *)tc_ptr;
373 #if defined(__sparc__)
374 __asm__ __volatile__("call %0\n\t"
378 : "i0", "i1", "i2", "i3", "i4", "i5");
379 #elif defined(__arm__)
380 asm volatile ("mov pc, %0\n\t"
381 ".global exec_loop\n\t"
385 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
389 env->current_tb = NULL;
390 /* reset soft MMU for next block (it can currently
391 only be set by a memory fault) */
392 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
393 if (env->hflags & HF_SOFTMMU_MASK) {
394 env->hflags &= ~HF_SOFTMMU_MASK;
395 /* do not allow linking to another block */
405 #if defined(TARGET_I386)
406 /* restore flags in standard format */
407 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
409 /* restore global registers */
434 #elif defined(TARGET_ARM)
435 env->cpsr = compute_cpsr();
436 #elif defined(TARGET_SPARC)
437 #elif defined(TARGET_PPC)
439 #error unsupported target CPU
442 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
451 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
453 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
455 CPUX86State *saved_env;
459 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
461 cpu_x86_load_seg_cache(env, seg_reg, selector,
462 (uint8_t *)(selector << 4), 0xffff, 0);
464 load_seg(seg_reg, selector);
469 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
471 CPUX86State *saved_env;
476 helper_fsave(ptr, data32);
481 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
483 CPUX86State *saved_env;
488 helper_frstor(ptr, data32);
493 #endif /* TARGET_I386 */
505 #include <sys/ucontext.h>
507 #if defined(TARGET_I386)
509 /* 'pc' is the host PC at which the exception was raised. 'address' is
510 the effective address of the memory exception. 'is_write' is 1 if a
511 write caused the exception and otherwise 0'. 'old_set' is the
512 signal set which should be restored */
513 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
514 int is_write, sigset_t *old_set)
516 TranslationBlock *tb;
520 env = cpu_single_env; /* XXX: find a correct solution for multithread */
521 #if defined(DEBUG_SIGNAL)
522 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
523 pc, address, is_write, *(unsigned long *)old_set);
525 /* XXX: locking issue */
526 if (is_write && page_unprotect(address)) {
529 /* see if it is an MMU fault */
530 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
531 ((env->hflags & HF_CPL_MASK) == 3), 0);
533 return 0; /* not an MMU fault */
535 return 1; /* the MMU fault was handled without causing real CPU fault */
536 /* now we have a real cpu fault */
539 /* the PC is inside the translated code. It means that we have
540 a virtual CPU fault */
541 cpu_restore_state(tb, env, pc);
545 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
546 env->eip, env->cr[2], env->error_code);
548 /* we restore the process signal mask as the sigreturn should
549 do it (XXX: use sigsetjmp) */
550 sigprocmask(SIG_SETMASK, old_set, NULL);
551 raise_exception_err(EXCP0E_PAGE, env->error_code);
553 /* activate soft MMU for this block */
554 env->hflags |= HF_SOFTMMU_MASK;
555 sigprocmask(SIG_SETMASK, old_set, NULL);
558 /* never comes here */
562 #elif defined(TARGET_ARM)
563 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
564 int is_write, sigset_t *old_set)
569 #elif defined(TARGET_SPARC)
570 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
571 int is_write, sigset_t *old_set)
573 /* XXX: locking issue */
574 if (is_write && page_unprotect(address)) {
579 #elif defined (TARGET_PPC)
580 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
581 int is_write, sigset_t *old_set)
583 TranslationBlock *tb;
588 env = cpu_single_env; /* XXX: find a correct solution for multithread */
590 #if defined(DEBUG_SIGNAL)
591 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
592 pc, address, is_write, *(unsigned long *)old_set);
594 /* XXX: locking issue */
595 if (is_write && page_unprotect(address)) {
599 /* see if it is an MMU fault */
600 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
602 return 0; /* not an MMU fault */
604 return 1; /* the MMU fault was handled without causing real CPU fault */
606 /* now we have a real cpu fault */
609 /* the PC is inside the translated code. It means that we have
610 a virtual CPU fault */
611 cpu_restore_state(tb, env, pc);
615 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
616 env->nip, env->error_code, tb);
618 /* we restore the process signal mask as the sigreturn should
619 do it (XXX: use sigsetjmp) */
620 sigprocmask(SIG_SETMASK, old_set, NULL);
621 do_queue_exception_err(env->exception_index, env->error_code);
623 /* activate soft MMU for this block */
624 sigprocmask(SIG_SETMASK, old_set, NULL);
627 /* never comes here */
631 #error unsupported target CPU
634 #if defined(__i386__)
636 int cpu_signal_handler(int host_signum, struct siginfo *info,
639 struct ucontext *uc = puc;
646 #define REG_TRAPNO TRAPNO
648 pc = uc->uc_mcontext.gregs[REG_EIP];
649 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
650 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
651 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
655 #elif defined(__powerpc)
657 int cpu_signal_handler(int host_signum, struct siginfo *info,
660 struct ucontext *uc = puc;
661 struct pt_regs *regs = uc->uc_mcontext.regs;
669 if (regs->dsisr & 0x00800000)
672 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
675 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
676 is_write, &uc->uc_sigmask);
679 #elif defined(__alpha__)
681 int cpu_signal_handler(int host_signum, struct siginfo *info,
684 struct ucontext *uc = puc;
685 uint32_t *pc = uc->uc_mcontext.sc_pc;
689 /* XXX: need kernel patch to get write flag faster */
690 switch (insn >> 26) {
705 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
706 is_write, &uc->uc_sigmask);
708 #elif defined(__sparc__)
710 int cpu_signal_handler(int host_signum, struct siginfo *info,
713 uint32_t *regs = (uint32_t *)(info + 1);
714 void *sigmask = (regs + 20);
719 /* XXX: is there a standard glibc define ? */
721 /* XXX: need kernel patch to get write flag faster */
723 insn = *(uint32_t *)pc;
724 if ((insn >> 30) == 3) {
725 switch((insn >> 19) & 0x3f) {
737 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
741 #elif defined(__arm__)
743 int cpu_signal_handler(int host_signum, struct siginfo *info,
746 struct ucontext *uc = puc;
750 pc = uc->uc_mcontext.gregs[R15];
751 /* XXX: compute is_write */
753 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
758 #elif defined(__mc68000)
760 int cpu_signal_handler(int host_signum, struct siginfo *info,
763 struct ucontext *uc = puc;
767 pc = uc->uc_mcontext.gregs[16];
768 /* XXX: compute is_write */
770 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
777 #error host CPU specific signal handler needed