2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env->jmp_env, 1);
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
73 longjmp(env->jmp_env, 1);
77 static TranslationBlock *tb_find_slow(target_ulong pc,
81 TranslationBlock *tb, **ptb1;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
89 tb_invalidated_flag = 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
118 ptb1 = &tb->phys_hash_next;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
131 tc_ptr = code_gen_ptr;
133 tb->cs_base = cs_base;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
144 tb_link_phys(tb, phys_pc, phys_page2);
147 if (tb_invalidated_flag) {
148 /* as some TB could have been invalidated because
149 of memory exceptions while generating the code, we
150 must recompute the hash index here */
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
159 static inline TranslationBlock *tb_find_fast(void)
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
168 #if defined(TARGET_I386)
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 cs_base = env->segs[R_CS].base;
172 pc = cs_base + env->eip;
173 #elif defined(TARGET_ARM)
174 flags = env->thumb | (env->vfp.vec_len << 1)
175 | (env->vfp.vec_stride << 4);
178 #elif defined(TARGET_SPARC)
179 #ifdef TARGET_SPARC64
180 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
182 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
186 #elif defined(TARGET_PPC)
187 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
188 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 #elif defined(TARGET_MIPS)
192 flags = env->hflags & MIPS_HFLAGS_TMASK;
196 #error unsupported CPU
198 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
199 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
200 tb->flags != flags, 0)) {
201 tb = tb_find_slow(pc, cs_base, flags);
207 /* main execution loop */
209 int cpu_exec(CPUState *env1)
211 int saved_T0, saved_T1;
216 #if defined(TARGET_I386)
241 #elif defined(TARGET_SPARC)
242 #if defined(reg_REGWPTR)
243 uint32_t *saved_regwptr;
247 int saved_i7, tmp_T0;
249 int ret, interrupt_request;
250 void (*gen_func)(void);
251 TranslationBlock *tb;
254 /* first we save global registers */
263 /* we also save i7 because longjmp may not restore it */
264 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
267 #if defined(TARGET_I386)
294 /* put eflags in CPU temporary format */
295 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
296 DF = 1 - (2 * ((env->eflags >> 10) & 1));
297 CC_OP = CC_OP_EFLAGS;
298 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
299 #elif defined(TARGET_ARM)
303 env->CF = (psr >> 29) & 1;
304 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
305 env->VF = (psr << 3) & 0x80000000;
306 env->QF = (psr >> 27) & 1;
307 env->cpsr = psr & ~CACHED_CPSR_BITS;
309 #elif defined(TARGET_SPARC)
310 #if defined(reg_REGWPTR)
311 saved_regwptr = REGWPTR;
313 #elif defined(TARGET_PPC)
314 #elif defined(TARGET_MIPS)
316 #error unsupported target CPU
318 env->exception_index = -1;
320 /* prepare setjmp context for exception handling */
322 if (setjmp(env->jmp_env) == 0) {
323 env->current_tb = NULL;
324 /* if an exception is pending, we execute it here */
325 if (env->exception_index >= 0) {
326 if (env->exception_index >= EXCP_INTERRUPT) {
327 /* exit request from the cpu execution loop */
328 ret = env->exception_index;
330 } else if (env->user_mode_only) {
331 /* if user mode only, we simulate a fake exception
332 which will be hanlded outside the cpu execution
334 #if defined(TARGET_I386)
335 do_interrupt_user(env->exception_index,
336 env->exception_is_int,
338 env->exception_next_eip);
340 ret = env->exception_index;
343 #if defined(TARGET_I386)
344 /* simulate a real cpu exception. On i386, it can
345 trigger new exceptions, but we do not handle
346 double or triple faults yet. */
347 do_interrupt(env->exception_index,
348 env->exception_is_int,
350 env->exception_next_eip, 0);
351 #elif defined(TARGET_PPC)
353 #elif defined(TARGET_MIPS)
355 #elif defined(TARGET_SPARC)
356 do_interrupt(env->exception_index);
359 env->exception_index = -1;
362 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
364 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
365 ret = kqemu_cpu_exec(env);
366 /* put eflags in CPU temporary format */
367 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
368 DF = 1 - (2 * ((env->eflags >> 10) & 1));
369 CC_OP = CC_OP_EFLAGS;
370 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
373 longjmp(env->jmp_env, 1);
374 } else if (ret == 2) {
375 /* softmmu execution needed */
377 if (env->interrupt_request != 0) {
378 /* hardware interrupt will be executed just after */
380 /* otherwise, we restart */
381 longjmp(env->jmp_env, 1);
387 T0 = 0; /* force lookup of first TB */
390 /* g1 can be modified by some libc? functions */
393 interrupt_request = env->interrupt_request;
394 if (__builtin_expect(interrupt_request, 0)) {
395 #if defined(TARGET_I386)
396 /* if hardware interrupt pending, we execute it */
397 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
398 (env->eflags & IF_MASK) &&
399 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
401 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
402 intno = cpu_get_pic_interrupt(env);
403 if (loglevel & CPU_LOG_TB_IN_ASM) {
404 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
406 do_interrupt(intno, 0, 0, 0, 1);
407 /* ensure that no TB jump will be modified as
408 the program flow was changed */
415 #elif defined(TARGET_PPC)
417 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
422 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
424 env->exception_index = EXCP_EXTERNAL;
427 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
433 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
435 env->exception_index = EXCP_DECR;
438 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
446 #elif defined(TARGET_MIPS)
447 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
448 (env->CP0_Status & (1 << CP0St_IE)) &&
449 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
450 !(env->hflags & MIPS_HFLAG_EXL) &&
451 !(env->hflags & MIPS_HFLAG_ERL) &&
452 !(env->hflags & MIPS_HFLAG_DM)) {
454 env->exception_index = EXCP_EXT_INTERRUPT;
457 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
464 #elif defined(TARGET_SPARC)
465 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
467 int pil = env->interrupt_index & 15;
468 int type = env->interrupt_index & 0xf0;
470 if (((type == TT_EXTINT) &&
471 (pil == 15 || pil > env->psrpil)) ||
473 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
474 do_interrupt(env->interrupt_index);
475 env->interrupt_index = 0;
482 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
483 //do_interrupt(0, 0, 0, 0, 0);
484 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
487 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
488 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
489 /* ensure that no TB jump will be modified as
490 the program flow was changed */
497 if (interrupt_request & CPU_INTERRUPT_EXIT) {
498 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
499 env->exception_index = EXCP_INTERRUPT;
504 if ((loglevel & CPU_LOG_EXEC)) {
505 #if defined(TARGET_I386)
506 /* restore flags in standard format */
508 env->regs[R_EAX] = EAX;
511 env->regs[R_EBX] = EBX;
514 env->regs[R_ECX] = ECX;
517 env->regs[R_EDX] = EDX;
520 env->regs[R_ESI] = ESI;
523 env->regs[R_EDI] = EDI;
526 env->regs[R_EBP] = EBP;
529 env->regs[R_ESP] = ESP;
531 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
532 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
533 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
534 #elif defined(TARGET_ARM)
535 env->cpsr = compute_cpsr();
536 cpu_dump_state(env, logfile, fprintf, 0);
537 env->cpsr &= ~CACHED_CPSR_BITS;
538 #elif defined(TARGET_SPARC)
539 REGWPTR = env->regbase + (env->cwp * 16);
540 env->regwptr = REGWPTR;
541 cpu_dump_state(env, logfile, fprintf, 0);
542 #elif defined(TARGET_PPC)
543 cpu_dump_state(env, logfile, fprintf, 0);
544 #elif defined(TARGET_MIPS)
545 cpu_dump_state(env, logfile, fprintf, 0);
547 #error unsupported target CPU
553 if ((loglevel & CPU_LOG_EXEC)) {
554 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
555 (long)tb->tc_ptr, tb->pc,
556 lookup_symbol(tb->pc));
562 /* see if we can patch the calling TB. When the TB
563 spans two pages, we cannot safely do a direct
567 tb->page_addr[1] == -1
568 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
569 && (tb->cflags & CF_CODE_COPY) ==
570 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
574 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
575 #if defined(USE_CODE_COPY)
576 /* propagates the FP use info */
577 ((TranslationBlock *)(T0 & ~3))->cflags |=
578 (tb->cflags & CF_FP_USED);
580 spin_unlock(&tb_lock);
584 env->current_tb = tb;
585 /* execute the generated code */
586 gen_func = (void *)tc_ptr;
587 #if defined(__sparc__)
588 __asm__ __volatile__("call %0\n\t"
592 : "i0", "i1", "i2", "i3", "i4", "i5");
593 #elif defined(__arm__)
594 asm volatile ("mov pc, %0\n\t"
595 ".global exec_loop\n\t"
599 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
600 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
602 if (!(tb->cflags & CF_CODE_COPY)) {
603 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
604 save_native_fp_state(env);
608 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
609 restore_native_fp_state(env);
611 /* we work with native eflags */
612 CC_SRC = cc_table[CC_OP].compute_all();
613 CC_OP = CC_OP_EFLAGS;
614 asm(".globl exec_loop\n"
619 " fs movl %11, %%eax\n"
620 " andl $0x400, %%eax\n"
621 " fs orl %8, %%eax\n"
624 " fs movl %%esp, %12\n"
625 " fs movl %0, %%eax\n"
626 " fs movl %1, %%ecx\n"
627 " fs movl %2, %%edx\n"
628 " fs movl %3, %%ebx\n"
629 " fs movl %4, %%esp\n"
630 " fs movl %5, %%ebp\n"
631 " fs movl %6, %%esi\n"
632 " fs movl %7, %%edi\n"
635 " fs movl %%esp, %4\n"
636 " fs movl %12, %%esp\n"
637 " fs movl %%eax, %0\n"
638 " fs movl %%ecx, %1\n"
639 " fs movl %%edx, %2\n"
640 " fs movl %%ebx, %3\n"
641 " fs movl %%ebp, %5\n"
642 " fs movl %%esi, %6\n"
643 " fs movl %%edi, %7\n"
646 " movl %%eax, %%ecx\n"
647 " andl $0x400, %%ecx\n"
649 " andl $0x8d5, %%eax\n"
650 " fs movl %%eax, %8\n"
652 " subl %%ecx, %%eax\n"
653 " fs movl %%eax, %11\n"
654 " fs movl %9, %%ebx\n" /* get T0 value */
657 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
658 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
659 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
660 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
661 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
662 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
663 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
664 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
665 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
666 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
668 "m" (*(uint8_t *)offsetof(CPUState, df)),
669 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
674 #elif defined(__ia64)
681 fp.gp = code_gen_buffer + 2 * (1 << 20);
682 (*(void (*)(void)) &fp)();
686 env->current_tb = NULL;
687 /* reset soft MMU for next block (it can currently
688 only be set by a memory fault) */
689 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
690 if (env->hflags & HF_SOFTMMU_MASK) {
691 env->hflags &= ~HF_SOFTMMU_MASK;
692 /* do not allow linking to another block */
703 #if defined(TARGET_I386)
704 #if defined(USE_CODE_COPY)
705 if (env->native_fp_regs) {
706 save_native_fp_state(env);
709 /* restore flags in standard format */
710 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
712 /* restore global registers */
737 #elif defined(TARGET_ARM)
738 env->cpsr = compute_cpsr();
739 /* XXX: Save/restore host fpu exception state?. */
740 #elif defined(TARGET_SPARC)
741 #if defined(reg_REGWPTR)
742 REGWPTR = saved_regwptr;
744 #elif defined(TARGET_PPC)
745 #elif defined(TARGET_MIPS)
747 #error unsupported target CPU
750 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
761 /* must only be called from the generated code as an exception can be
763 void tb_invalidate_page_range(target_ulong start, target_ulong end)
765 /* XXX: cannot enable it yet because it yields to MMU exception
766 where NIP != read address on PowerPC */
768 target_ulong phys_addr;
769 phys_addr = get_phys_addr_code(env, start);
770 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
774 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
776 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
778 CPUX86State *saved_env;
782 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
784 cpu_x86_load_seg_cache(env, seg_reg, selector,
785 (selector << 4), 0xffff, 0);
787 load_seg(seg_reg, selector);
792 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
794 CPUX86State *saved_env;
799 helper_fsave((target_ulong)ptr, data32);
804 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
806 CPUX86State *saved_env;
811 helper_frstor((target_ulong)ptr, data32);
816 #endif /* TARGET_I386 */
818 #if !defined(CONFIG_SOFTMMU)
820 #if defined(TARGET_I386)
822 /* 'pc' is the host PC at which the exception was raised. 'address' is
823 the effective address of the memory exception. 'is_write' is 1 if a
824 write caused the exception and otherwise 0'. 'old_set' is the
825 signal set which should be restored */
826 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
827 int is_write, sigset_t *old_set,
830 TranslationBlock *tb;
834 env = cpu_single_env; /* XXX: find a correct solution for multithread */
835 #if defined(DEBUG_SIGNAL)
836 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
837 pc, address, is_write, *(unsigned long *)old_set);
839 /* XXX: locking issue */
840 if (is_write && page_unprotect(address, pc, puc)) {
844 /* see if it is an MMU fault */
845 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
846 ((env->hflags & HF_CPL_MASK) == 3), 0);
848 return 0; /* not an MMU fault */
850 return 1; /* the MMU fault was handled without causing real CPU fault */
851 /* now we have a real cpu fault */
854 /* the PC is inside the translated code. It means that we have
855 a virtual CPU fault */
856 cpu_restore_state(tb, env, pc, puc);
860 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
861 env->eip, env->cr[2], env->error_code);
863 /* we restore the process signal mask as the sigreturn should
864 do it (XXX: use sigsetjmp) */
865 sigprocmask(SIG_SETMASK, old_set, NULL);
866 raise_exception_err(EXCP0E_PAGE, env->error_code);
868 /* activate soft MMU for this block */
869 env->hflags |= HF_SOFTMMU_MASK;
870 cpu_resume_from_signal(env, puc);
872 /* never comes here */
876 #elif defined(TARGET_ARM)
877 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
878 int is_write, sigset_t *old_set,
881 TranslationBlock *tb;
885 env = cpu_single_env; /* XXX: find a correct solution for multithread */
886 #if defined(DEBUG_SIGNAL)
887 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
888 pc, address, is_write, *(unsigned long *)old_set);
890 /* XXX: locking issue */
891 if (is_write && page_unprotect(address, pc, puc)) {
894 /* see if it is an MMU fault */
895 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
897 return 0; /* not an MMU fault */
899 return 1; /* the MMU fault was handled without causing real CPU fault */
900 /* now we have a real cpu fault */
903 /* the PC is inside the translated code. It means that we have
904 a virtual CPU fault */
905 cpu_restore_state(tb, env, pc, puc);
907 /* we restore the process signal mask as the sigreturn should
908 do it (XXX: use sigsetjmp) */
909 sigprocmask(SIG_SETMASK, old_set, NULL);
912 #elif defined(TARGET_SPARC)
913 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
914 int is_write, sigset_t *old_set,
917 TranslationBlock *tb;
921 env = cpu_single_env; /* XXX: find a correct solution for multithread */
922 #if defined(DEBUG_SIGNAL)
923 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
924 pc, address, is_write, *(unsigned long *)old_set);
926 /* XXX: locking issue */
927 if (is_write && page_unprotect(address, pc, puc)) {
930 /* see if it is an MMU fault */
931 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
933 return 0; /* not an MMU fault */
935 return 1; /* the MMU fault was handled without causing real CPU fault */
936 /* now we have a real cpu fault */
939 /* the PC is inside the translated code. It means that we have
940 a virtual CPU fault */
941 cpu_restore_state(tb, env, pc, puc);
943 /* we restore the process signal mask as the sigreturn should
944 do it (XXX: use sigsetjmp) */
945 sigprocmask(SIG_SETMASK, old_set, NULL);
948 #elif defined (TARGET_PPC)
949 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
950 int is_write, sigset_t *old_set,
953 TranslationBlock *tb;
957 env = cpu_single_env; /* XXX: find a correct solution for multithread */
958 #if defined(DEBUG_SIGNAL)
959 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
960 pc, address, is_write, *(unsigned long *)old_set);
962 /* XXX: locking issue */
963 if (is_write && page_unprotect(address, pc, puc)) {
967 /* see if it is an MMU fault */
968 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
970 return 0; /* not an MMU fault */
972 return 1; /* the MMU fault was handled without causing real CPU fault */
974 /* now we have a real cpu fault */
977 /* the PC is inside the translated code. It means that we have
978 a virtual CPU fault */
979 cpu_restore_state(tb, env, pc, puc);
983 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
984 env->nip, env->error_code, tb);
986 /* we restore the process signal mask as the sigreturn should
987 do it (XXX: use sigsetjmp) */
988 sigprocmask(SIG_SETMASK, old_set, NULL);
989 do_raise_exception_err(env->exception_index, env->error_code);
991 /* activate soft MMU for this block */
992 cpu_resume_from_signal(env, puc);
994 /* never comes here */
998 #elif defined (TARGET_MIPS)
999 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1000 int is_write, sigset_t *old_set,
1003 TranslationBlock *tb;
1007 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1008 #if defined(DEBUG_SIGNAL)
1009 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1010 pc, address, is_write, *(unsigned long *)old_set);
1012 /* XXX: locking issue */
1013 if (is_write && page_unprotect(address, pc, puc)) {
1017 /* see if it is an MMU fault */
1018 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1020 return 0; /* not an MMU fault */
1022 return 1; /* the MMU fault was handled without causing real CPU fault */
1024 /* now we have a real cpu fault */
1025 tb = tb_find_pc(pc);
1027 /* the PC is inside the translated code. It means that we have
1028 a virtual CPU fault */
1029 cpu_restore_state(tb, env, pc, puc);
1033 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1034 env->nip, env->error_code, tb);
1036 /* we restore the process signal mask as the sigreturn should
1037 do it (XXX: use sigsetjmp) */
1038 sigprocmask(SIG_SETMASK, old_set, NULL);
1039 do_raise_exception_err(env->exception_index, env->error_code);
1041 /* activate soft MMU for this block */
1042 cpu_resume_from_signal(env, puc);
1044 /* never comes here */
1049 #error unsupported target CPU
1052 #if defined(__i386__)
1054 #if defined(USE_CODE_COPY)
1055 static void cpu_send_trap(unsigned long pc, int trap,
1056 struct ucontext *uc)
1058 TranslationBlock *tb;
1061 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1062 /* now we have a real cpu fault */
1063 tb = tb_find_pc(pc);
1065 /* the PC is inside the translated code. It means that we have
1066 a virtual CPU fault */
1067 cpu_restore_state(tb, env, pc, uc);
1069 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1070 raise_exception_err(trap, env->error_code);
1074 int cpu_signal_handler(int host_signum, struct siginfo *info,
1077 struct ucontext *uc = puc;
1085 #define REG_TRAPNO TRAPNO
1087 pc = uc->uc_mcontext.gregs[REG_EIP];
1088 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1089 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1090 if (trapno == 0x00 || trapno == 0x05) {
1091 /* send division by zero or bound exception */
1092 cpu_send_trap(pc, trapno, uc);
1096 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1098 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1099 &uc->uc_sigmask, puc);
1102 #elif defined(__x86_64__)
1104 int cpu_signal_handler(int host_signum, struct siginfo *info,
1107 struct ucontext *uc = puc;
1110 pc = uc->uc_mcontext.gregs[REG_RIP];
1111 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1112 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1113 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1114 &uc->uc_sigmask, puc);
1117 #elif defined(__powerpc__)
1119 /***********************************************************************
1120 * signal context platform-specific definitions
1124 /* All Registers access - only for local access */
1125 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1126 /* Gpr Registers access */
1127 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1128 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1129 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1130 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1131 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1132 # define LR_sig(context) REG_sig(link, context) /* Link register */
1133 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1134 /* Float Registers access */
1135 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1136 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1137 /* Exception Registers access */
1138 # define DAR_sig(context) REG_sig(dar, context)
1139 # define DSISR_sig(context) REG_sig(dsisr, context)
1140 # define TRAP_sig(context) REG_sig(trap, context)
1144 # include <sys/ucontext.h>
1145 typedef struct ucontext SIGCONTEXT;
1146 /* All Registers access - only for local access */
1147 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1148 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1149 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1150 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1151 /* Gpr Registers access */
1152 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1153 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1154 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1155 # define CTR_sig(context) REG_sig(ctr, context)
1156 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1157 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1158 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1159 /* Float Registers access */
1160 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1161 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1162 /* Exception Registers access */
1163 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1164 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1165 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1166 #endif /* __APPLE__ */
1168 int cpu_signal_handler(int host_signum, struct siginfo *info,
1171 struct ucontext *uc = puc;
1179 if (DSISR_sig(uc) & 0x00800000)
1182 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1185 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1186 is_write, &uc->uc_sigmask, puc);
1189 #elif defined(__alpha__)
1191 int cpu_signal_handler(int host_signum, struct siginfo *info,
1194 struct ucontext *uc = puc;
1195 uint32_t *pc = uc->uc_mcontext.sc_pc;
1196 uint32_t insn = *pc;
1199 /* XXX: need kernel patch to get write flag faster */
1200 switch (insn >> 26) {
1215 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1216 is_write, &uc->uc_sigmask, puc);
1218 #elif defined(__sparc__)
1220 int cpu_signal_handler(int host_signum, struct siginfo *info,
1223 uint32_t *regs = (uint32_t *)(info + 1);
1224 void *sigmask = (regs + 20);
1229 /* XXX: is there a standard glibc define ? */
1231 /* XXX: need kernel patch to get write flag faster */
1233 insn = *(uint32_t *)pc;
1234 if ((insn >> 30) == 3) {
1235 switch((insn >> 19) & 0x3f) {
1247 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1248 is_write, sigmask, NULL);
1251 #elif defined(__arm__)
1253 int cpu_signal_handler(int host_signum, struct siginfo *info,
1256 struct ucontext *uc = puc;
1260 pc = uc->uc_mcontext.gregs[R15];
1261 /* XXX: compute is_write */
1263 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1268 #elif defined(__mc68000)
1270 int cpu_signal_handler(int host_signum, struct siginfo *info,
1273 struct ucontext *uc = puc;
1277 pc = uc->uc_mcontext.gregs[16];
1278 /* XXX: compute is_write */
1280 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1282 &uc->uc_sigmask, puc);
1285 #elif defined(__ia64)
1288 /* This ought to be in <bits/siginfo.h>... */
1289 # define __ISR_VALID 1
1290 # define si_flags _sifields._sigfault._si_pad0
1293 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1295 struct ucontext *uc = puc;
1299 ip = uc->uc_mcontext.sc_ip;
1300 switch (host_signum) {
1306 if (info->si_code && (info->si_flags & __ISR_VALID))
1307 /* ISR.W (write-access) is bit 33: */
1308 is_write = (info->si_isr >> 33) & 1;
1314 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1316 &uc->uc_sigmask, puc);
1319 #elif defined(__s390__)
1321 int cpu_signal_handler(int host_signum, struct siginfo *info,
1324 struct ucontext *uc = puc;
1328 pc = uc->uc_mcontext.psw.addr;
1329 /* XXX: compute is_write */
1331 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1333 &uc->uc_sigmask, puc);
1338 #error host CPU specific signal handler needed
1342 #endif /* !defined(CONFIG_SOFTMMU) */