2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env->jmp_env, 1);
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
73 longjmp(env->jmp_env, 1);
77 static TranslationBlock *tb_find_slow(target_ulong pc,
81 TranslationBlock *tb, **ptb1;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
89 tb_invalidated_flag = 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
118 ptb1 = &tb->phys_hash_next;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
131 tc_ptr = code_gen_ptr;
133 tb->cs_base = cs_base;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
144 tb_link_phys(tb, phys_pc, phys_page2);
147 if (tb_invalidated_flag) {
148 /* as some TB could have been invalidated because
149 of memory exceptions while generating the code, we
150 must recompute the hash index here */
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
159 static inline TranslationBlock *tb_find_fast(void)
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
168 #if defined(TARGET_I386)
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 cs_base = env->segs[R_CS].base;
172 pc = cs_base + env->eip;
173 #elif defined(TARGET_ARM)
174 flags = env->thumb | (env->vfp.vec_len << 1)
175 | (env->vfp.vec_stride << 4);
178 #elif defined(TARGET_SPARC)
179 #ifdef TARGET_SPARC64
180 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
182 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
186 #elif defined(TARGET_PPC)
187 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
188 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 #elif defined(TARGET_MIPS)
192 flags = env->hflags & MIPS_HFLAGS_TMASK;
196 #error unsupported CPU
198 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
199 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
200 tb->flags != flags, 0)) {
201 tb = tb_find_slow(pc, cs_base, flags);
207 /* main execution loop */
209 int cpu_exec(CPUState *env1)
211 int saved_T0, saved_T1;
216 #if defined(TARGET_I386)
241 #elif defined(TARGET_SPARC)
242 #if defined(reg_REGWPTR)
243 uint32_t *saved_regwptr;
247 int saved_i7, tmp_T0;
249 int ret, interrupt_request;
250 void (*gen_func)(void);
251 TranslationBlock *tb;
254 #if defined(TARGET_I386)
255 /* handle exit of HALTED state */
256 if (env1->hflags & HF_HALTED_MASK) {
257 /* disable halt condition */
258 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
259 (env1->eflags & IF_MASK)) {
260 env1->hflags &= ~HF_HALTED_MASK;
265 #elif defined(TARGET_PPC)
266 if (env1->msr[MSR_POW]) {
267 if (env1->msr[MSR_EE] &&
268 (env1->interrupt_request &
269 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
270 env1->msr[MSR_POW] = 0;
277 cpu_single_env = env1;
279 /* first we save global registers */
288 /* we also save i7 because longjmp may not restore it */
289 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
292 #if defined(TARGET_I386)
319 /* put eflags in CPU temporary format */
320 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
321 DF = 1 - (2 * ((env->eflags >> 10) & 1));
322 CC_OP = CC_OP_EFLAGS;
323 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
324 #elif defined(TARGET_ARM)
328 env->CF = (psr >> 29) & 1;
329 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
330 env->VF = (psr << 3) & 0x80000000;
331 env->QF = (psr >> 27) & 1;
332 env->cpsr = psr & ~CACHED_CPSR_BITS;
334 #elif defined(TARGET_SPARC)
335 #if defined(reg_REGWPTR)
336 saved_regwptr = REGWPTR;
338 #elif defined(TARGET_PPC)
339 #elif defined(TARGET_MIPS)
341 #error unsupported target CPU
343 env->exception_index = -1;
345 /* prepare setjmp context for exception handling */
347 if (setjmp(env->jmp_env) == 0) {
348 env->current_tb = NULL;
349 /* if an exception is pending, we execute it here */
350 if (env->exception_index >= 0) {
351 if (env->exception_index >= EXCP_INTERRUPT) {
352 /* exit request from the cpu execution loop */
353 ret = env->exception_index;
355 } else if (env->user_mode_only) {
356 /* if user mode only, we simulate a fake exception
357 which will be hanlded outside the cpu execution
359 #if defined(TARGET_I386)
360 do_interrupt_user(env->exception_index,
361 env->exception_is_int,
363 env->exception_next_eip);
365 ret = env->exception_index;
368 #if defined(TARGET_I386)
369 /* simulate a real cpu exception. On i386, it can
370 trigger new exceptions, but we do not handle
371 double or triple faults yet. */
372 do_interrupt(env->exception_index,
373 env->exception_is_int,
375 env->exception_next_eip, 0);
376 #elif defined(TARGET_PPC)
378 #elif defined(TARGET_MIPS)
380 #elif defined(TARGET_SPARC)
381 do_interrupt(env->exception_index);
384 env->exception_index = -1;
387 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
389 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
390 ret = kqemu_cpu_exec(env);
391 /* put eflags in CPU temporary format */
392 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
393 DF = 1 - (2 * ((env->eflags >> 10) & 1));
394 CC_OP = CC_OP_EFLAGS;
395 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
398 longjmp(env->jmp_env, 1);
399 } else if (ret == 2) {
400 /* softmmu execution needed */
402 if (env->interrupt_request != 0) {
403 /* hardware interrupt will be executed just after */
405 /* otherwise, we restart */
406 longjmp(env->jmp_env, 1);
412 T0 = 0; /* force lookup of first TB */
415 /* g1 can be modified by some libc? functions */
418 interrupt_request = env->interrupt_request;
419 if (__builtin_expect(interrupt_request, 0)) {
420 #if defined(TARGET_I386)
421 /* if hardware interrupt pending, we execute it */
422 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
423 (env->eflags & IF_MASK) &&
424 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
426 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
427 intno = cpu_get_pic_interrupt(env);
428 if (loglevel & CPU_LOG_TB_IN_ASM) {
429 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
431 do_interrupt(intno, 0, 0, 0, 1);
432 /* ensure that no TB jump will be modified as
433 the program flow was changed */
440 #elif defined(TARGET_PPC)
442 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
447 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
449 env->exception_index = EXCP_EXTERNAL;
452 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
458 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
460 env->exception_index = EXCP_DECR;
463 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
471 #elif defined(TARGET_MIPS)
472 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
473 (env->CP0_Status & (1 << CP0St_IE)) &&
474 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
475 !(env->hflags & MIPS_HFLAG_EXL) &&
476 !(env->hflags & MIPS_HFLAG_ERL) &&
477 !(env->hflags & MIPS_HFLAG_DM)) {
479 env->exception_index = EXCP_EXT_INTERRUPT;
482 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
489 #elif defined(TARGET_SPARC)
490 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
492 int pil = env->interrupt_index & 15;
493 int type = env->interrupt_index & 0xf0;
495 if (((type == TT_EXTINT) &&
496 (pil == 15 || pil > env->psrpil)) ||
498 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
499 do_interrupt(env->interrupt_index);
500 env->interrupt_index = 0;
507 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
508 //do_interrupt(0, 0, 0, 0, 0);
509 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
512 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
513 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
514 /* ensure that no TB jump will be modified as
515 the program flow was changed */
522 if (interrupt_request & CPU_INTERRUPT_EXIT) {
523 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
524 env->exception_index = EXCP_INTERRUPT;
529 if ((loglevel & CPU_LOG_EXEC)) {
530 #if defined(TARGET_I386)
531 /* restore flags in standard format */
533 env->regs[R_EAX] = EAX;
536 env->regs[R_EBX] = EBX;
539 env->regs[R_ECX] = ECX;
542 env->regs[R_EDX] = EDX;
545 env->regs[R_ESI] = ESI;
548 env->regs[R_EDI] = EDI;
551 env->regs[R_EBP] = EBP;
554 env->regs[R_ESP] = ESP;
556 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
557 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
558 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
559 #elif defined(TARGET_ARM)
560 env->cpsr = compute_cpsr();
561 cpu_dump_state(env, logfile, fprintf, 0);
562 env->cpsr &= ~CACHED_CPSR_BITS;
563 #elif defined(TARGET_SPARC)
564 REGWPTR = env->regbase + (env->cwp * 16);
565 env->regwptr = REGWPTR;
566 cpu_dump_state(env, logfile, fprintf, 0);
567 #elif defined(TARGET_PPC)
568 cpu_dump_state(env, logfile, fprintf, 0);
569 #elif defined(TARGET_MIPS)
570 cpu_dump_state(env, logfile, fprintf, 0);
572 #error unsupported target CPU
578 if ((loglevel & CPU_LOG_EXEC)) {
579 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
580 (long)tb->tc_ptr, tb->pc,
581 lookup_symbol(tb->pc));
587 /* see if we can patch the calling TB. When the TB
588 spans two pages, we cannot safely do a direct
592 tb->page_addr[1] == -1
593 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
594 && (tb->cflags & CF_CODE_COPY) ==
595 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
599 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
600 #if defined(USE_CODE_COPY)
601 /* propagates the FP use info */
602 ((TranslationBlock *)(T0 & ~3))->cflags |=
603 (tb->cflags & CF_FP_USED);
605 spin_unlock(&tb_lock);
609 env->current_tb = tb;
610 /* execute the generated code */
611 gen_func = (void *)tc_ptr;
612 #if defined(__sparc__)
613 __asm__ __volatile__("call %0\n\t"
617 : "i0", "i1", "i2", "i3", "i4", "i5");
618 #elif defined(__arm__)
619 asm volatile ("mov pc, %0\n\t"
620 ".global exec_loop\n\t"
624 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
625 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
627 if (!(tb->cflags & CF_CODE_COPY)) {
628 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
629 save_native_fp_state(env);
633 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
634 restore_native_fp_state(env);
636 /* we work with native eflags */
637 CC_SRC = cc_table[CC_OP].compute_all();
638 CC_OP = CC_OP_EFLAGS;
639 asm(".globl exec_loop\n"
644 " fs movl %11, %%eax\n"
645 " andl $0x400, %%eax\n"
646 " fs orl %8, %%eax\n"
649 " fs movl %%esp, %12\n"
650 " fs movl %0, %%eax\n"
651 " fs movl %1, %%ecx\n"
652 " fs movl %2, %%edx\n"
653 " fs movl %3, %%ebx\n"
654 " fs movl %4, %%esp\n"
655 " fs movl %5, %%ebp\n"
656 " fs movl %6, %%esi\n"
657 " fs movl %7, %%edi\n"
660 " fs movl %%esp, %4\n"
661 " fs movl %12, %%esp\n"
662 " fs movl %%eax, %0\n"
663 " fs movl %%ecx, %1\n"
664 " fs movl %%edx, %2\n"
665 " fs movl %%ebx, %3\n"
666 " fs movl %%ebp, %5\n"
667 " fs movl %%esi, %6\n"
668 " fs movl %%edi, %7\n"
671 " movl %%eax, %%ecx\n"
672 " andl $0x400, %%ecx\n"
674 " andl $0x8d5, %%eax\n"
675 " fs movl %%eax, %8\n"
677 " subl %%ecx, %%eax\n"
678 " fs movl %%eax, %11\n"
679 " fs movl %9, %%ebx\n" /* get T0 value */
682 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
683 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
684 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
685 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
686 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
687 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
688 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
689 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
690 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
691 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
693 "m" (*(uint8_t *)offsetof(CPUState, df)),
694 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
699 #elif defined(__ia64)
706 fp.gp = code_gen_buffer + 2 * (1 << 20);
707 (*(void (*)(void)) &fp)();
711 env->current_tb = NULL;
712 /* reset soft MMU for next block (it can currently
713 only be set by a memory fault) */
714 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
715 if (env->hflags & HF_SOFTMMU_MASK) {
716 env->hflags &= ~HF_SOFTMMU_MASK;
717 /* do not allow linking to another block */
728 #if defined(TARGET_I386)
729 #if defined(USE_CODE_COPY)
730 if (env->native_fp_regs) {
731 save_native_fp_state(env);
734 /* restore flags in standard format */
735 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
737 /* restore global registers */
762 #elif defined(TARGET_ARM)
763 env->cpsr = compute_cpsr();
764 /* XXX: Save/restore host fpu exception state?. */
765 #elif defined(TARGET_SPARC)
766 #if defined(reg_REGWPTR)
767 REGWPTR = saved_regwptr;
769 #elif defined(TARGET_PPC)
770 #elif defined(TARGET_MIPS)
772 #error unsupported target CPU
775 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
783 /* fail safe : never use cpu_single_env outside cpu_exec() */
784 cpu_single_env = NULL;
788 /* must only be called from the generated code as an exception can be
790 void tb_invalidate_page_range(target_ulong start, target_ulong end)
792 /* XXX: cannot enable it yet because it yields to MMU exception
793 where NIP != read address on PowerPC */
795 target_ulong phys_addr;
796 phys_addr = get_phys_addr_code(env, start);
797 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
801 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
803 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
805 CPUX86State *saved_env;
809 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
811 cpu_x86_load_seg_cache(env, seg_reg, selector,
812 (selector << 4), 0xffff, 0);
814 load_seg(seg_reg, selector);
819 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
821 CPUX86State *saved_env;
826 helper_fsave((target_ulong)ptr, data32);
831 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
833 CPUX86State *saved_env;
838 helper_frstor((target_ulong)ptr, data32);
843 #endif /* TARGET_I386 */
845 #if !defined(CONFIG_SOFTMMU)
847 #if defined(TARGET_I386)
849 /* 'pc' is the host PC at which the exception was raised. 'address' is
850 the effective address of the memory exception. 'is_write' is 1 if a
851 write caused the exception and otherwise 0'. 'old_set' is the
852 signal set which should be restored */
853 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
854 int is_write, sigset_t *old_set,
857 TranslationBlock *tb;
861 env = cpu_single_env; /* XXX: find a correct solution for multithread */
862 #if defined(DEBUG_SIGNAL)
863 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
864 pc, address, is_write, *(unsigned long *)old_set);
866 /* XXX: locking issue */
867 if (is_write && page_unprotect(address, pc, puc)) {
871 /* see if it is an MMU fault */
872 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
873 ((env->hflags & HF_CPL_MASK) == 3), 0);
875 return 0; /* not an MMU fault */
877 return 1; /* the MMU fault was handled without causing real CPU fault */
878 /* now we have a real cpu fault */
881 /* the PC is inside the translated code. It means that we have
882 a virtual CPU fault */
883 cpu_restore_state(tb, env, pc, puc);
887 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
888 env->eip, env->cr[2], env->error_code);
890 /* we restore the process signal mask as the sigreturn should
891 do it (XXX: use sigsetjmp) */
892 sigprocmask(SIG_SETMASK, old_set, NULL);
893 raise_exception_err(EXCP0E_PAGE, env->error_code);
895 /* activate soft MMU for this block */
896 env->hflags |= HF_SOFTMMU_MASK;
897 cpu_resume_from_signal(env, puc);
899 /* never comes here */
903 #elif defined(TARGET_ARM)
904 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
905 int is_write, sigset_t *old_set,
908 TranslationBlock *tb;
912 env = cpu_single_env; /* XXX: find a correct solution for multithread */
913 #if defined(DEBUG_SIGNAL)
914 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
915 pc, address, is_write, *(unsigned long *)old_set);
917 /* XXX: locking issue */
918 if (is_write && page_unprotect(address, pc, puc)) {
921 /* see if it is an MMU fault */
922 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
924 return 0; /* not an MMU fault */
926 return 1; /* the MMU fault was handled without causing real CPU fault */
927 /* now we have a real cpu fault */
930 /* the PC is inside the translated code. It means that we have
931 a virtual CPU fault */
932 cpu_restore_state(tb, env, pc, puc);
934 /* we restore the process signal mask as the sigreturn should
935 do it (XXX: use sigsetjmp) */
936 sigprocmask(SIG_SETMASK, old_set, NULL);
939 #elif defined(TARGET_SPARC)
940 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
941 int is_write, sigset_t *old_set,
944 TranslationBlock *tb;
948 env = cpu_single_env; /* XXX: find a correct solution for multithread */
949 #if defined(DEBUG_SIGNAL)
950 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
951 pc, address, is_write, *(unsigned long *)old_set);
953 /* XXX: locking issue */
954 if (is_write && page_unprotect(address, pc, puc)) {
957 /* see if it is an MMU fault */
958 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
960 return 0; /* not an MMU fault */
962 return 1; /* the MMU fault was handled without causing real CPU fault */
963 /* now we have a real cpu fault */
966 /* the PC is inside the translated code. It means that we have
967 a virtual CPU fault */
968 cpu_restore_state(tb, env, pc, puc);
970 /* we restore the process signal mask as the sigreturn should
971 do it (XXX: use sigsetjmp) */
972 sigprocmask(SIG_SETMASK, old_set, NULL);
975 #elif defined (TARGET_PPC)
976 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
977 int is_write, sigset_t *old_set,
980 TranslationBlock *tb;
984 env = cpu_single_env; /* XXX: find a correct solution for multithread */
985 #if defined(DEBUG_SIGNAL)
986 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
987 pc, address, is_write, *(unsigned long *)old_set);
989 /* XXX: locking issue */
990 if (is_write && page_unprotect(address, pc, puc)) {
994 /* see if it is an MMU fault */
995 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
997 return 0; /* not an MMU fault */
999 return 1; /* the MMU fault was handled without causing real CPU fault */
1001 /* now we have a real cpu fault */
1002 tb = tb_find_pc(pc);
1004 /* the PC is inside the translated code. It means that we have
1005 a virtual CPU fault */
1006 cpu_restore_state(tb, env, pc, puc);
1010 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1011 env->nip, env->error_code, tb);
1013 /* we restore the process signal mask as the sigreturn should
1014 do it (XXX: use sigsetjmp) */
1015 sigprocmask(SIG_SETMASK, old_set, NULL);
1016 do_raise_exception_err(env->exception_index, env->error_code);
1018 /* activate soft MMU for this block */
1019 cpu_resume_from_signal(env, puc);
1021 /* never comes here */
1025 #elif defined (TARGET_MIPS)
1026 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1027 int is_write, sigset_t *old_set,
1030 TranslationBlock *tb;
1034 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1035 #if defined(DEBUG_SIGNAL)
1036 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1037 pc, address, is_write, *(unsigned long *)old_set);
1039 /* XXX: locking issue */
1040 if (is_write && page_unprotect(address, pc, puc)) {
1044 /* see if it is an MMU fault */
1045 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1047 return 0; /* not an MMU fault */
1049 return 1; /* the MMU fault was handled without causing real CPU fault */
1051 /* now we have a real cpu fault */
1052 tb = tb_find_pc(pc);
1054 /* the PC is inside the translated code. It means that we have
1055 a virtual CPU fault */
1056 cpu_restore_state(tb, env, pc, puc);
1060 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1061 env->nip, env->error_code, tb);
1063 /* we restore the process signal mask as the sigreturn should
1064 do it (XXX: use sigsetjmp) */
1065 sigprocmask(SIG_SETMASK, old_set, NULL);
1066 do_raise_exception_err(env->exception_index, env->error_code);
1068 /* activate soft MMU for this block */
1069 cpu_resume_from_signal(env, puc);
1071 /* never comes here */
1076 #error unsupported target CPU
1079 #if defined(__i386__)
1081 #if defined(USE_CODE_COPY)
1082 static void cpu_send_trap(unsigned long pc, int trap,
1083 struct ucontext *uc)
1085 TranslationBlock *tb;
1088 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1089 /* now we have a real cpu fault */
1090 tb = tb_find_pc(pc);
1092 /* the PC is inside the translated code. It means that we have
1093 a virtual CPU fault */
1094 cpu_restore_state(tb, env, pc, uc);
1096 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1097 raise_exception_err(trap, env->error_code);
1101 int cpu_signal_handler(int host_signum, struct siginfo *info,
1104 struct ucontext *uc = puc;
1112 #define REG_TRAPNO TRAPNO
1114 pc = uc->uc_mcontext.gregs[REG_EIP];
1115 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1116 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1117 if (trapno == 0x00 || trapno == 0x05) {
1118 /* send division by zero or bound exception */
1119 cpu_send_trap(pc, trapno, uc);
1123 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1125 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1126 &uc->uc_sigmask, puc);
1129 #elif defined(__x86_64__)
1131 int cpu_signal_handler(int host_signum, struct siginfo *info,
1134 struct ucontext *uc = puc;
1137 pc = uc->uc_mcontext.gregs[REG_RIP];
1138 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1139 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1140 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1141 &uc->uc_sigmask, puc);
1144 #elif defined(__powerpc__)
1146 /***********************************************************************
1147 * signal context platform-specific definitions
1151 /* All Registers access - only for local access */
1152 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1153 /* Gpr Registers access */
1154 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1155 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1156 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1157 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1158 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1159 # define LR_sig(context) REG_sig(link, context) /* Link register */
1160 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1161 /* Float Registers access */
1162 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1163 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1164 /* Exception Registers access */
1165 # define DAR_sig(context) REG_sig(dar, context)
1166 # define DSISR_sig(context) REG_sig(dsisr, context)
1167 # define TRAP_sig(context) REG_sig(trap, context)
1171 # include <sys/ucontext.h>
1172 typedef struct ucontext SIGCONTEXT;
1173 /* All Registers access - only for local access */
1174 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1175 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1176 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1177 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1178 /* Gpr Registers access */
1179 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1180 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1181 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1182 # define CTR_sig(context) REG_sig(ctr, context)
1183 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1184 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1185 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1186 /* Float Registers access */
1187 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1188 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1189 /* Exception Registers access */
1190 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1191 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1192 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1193 #endif /* __APPLE__ */
1195 int cpu_signal_handler(int host_signum, struct siginfo *info,
1198 struct ucontext *uc = puc;
1206 if (DSISR_sig(uc) & 0x00800000)
1209 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1212 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1213 is_write, &uc->uc_sigmask, puc);
1216 #elif defined(__alpha__)
1218 int cpu_signal_handler(int host_signum, struct siginfo *info,
1221 struct ucontext *uc = puc;
1222 uint32_t *pc = uc->uc_mcontext.sc_pc;
1223 uint32_t insn = *pc;
1226 /* XXX: need kernel patch to get write flag faster */
1227 switch (insn >> 26) {
1242 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1243 is_write, &uc->uc_sigmask, puc);
1245 #elif defined(__sparc__)
1247 int cpu_signal_handler(int host_signum, struct siginfo *info,
1250 uint32_t *regs = (uint32_t *)(info + 1);
1251 void *sigmask = (regs + 20);
1256 /* XXX: is there a standard glibc define ? */
1258 /* XXX: need kernel patch to get write flag faster */
1260 insn = *(uint32_t *)pc;
1261 if ((insn >> 30) == 3) {
1262 switch((insn >> 19) & 0x3f) {
1274 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1275 is_write, sigmask, NULL);
1278 #elif defined(__arm__)
1280 int cpu_signal_handler(int host_signum, struct siginfo *info,
1283 struct ucontext *uc = puc;
1287 pc = uc->uc_mcontext.gregs[R15];
1288 /* XXX: compute is_write */
1290 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1295 #elif defined(__mc68000)
1297 int cpu_signal_handler(int host_signum, struct siginfo *info,
1300 struct ucontext *uc = puc;
1304 pc = uc->uc_mcontext.gregs[16];
1305 /* XXX: compute is_write */
1307 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1309 &uc->uc_sigmask, puc);
1312 #elif defined(__ia64)
1315 /* This ought to be in <bits/siginfo.h>... */
1316 # define __ISR_VALID 1
1317 # define si_flags _sifields._sigfault._si_pad0
1320 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1322 struct ucontext *uc = puc;
1326 ip = uc->uc_mcontext.sc_ip;
1327 switch (host_signum) {
1333 if (info->si_code && (info->si_flags & __ISR_VALID))
1334 /* ISR.W (write-access) is bit 33: */
1335 is_write = (info->si_isr >> 33) & 1;
1341 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1343 &uc->uc_sigmask, puc);
1346 #elif defined(__s390__)
1348 int cpu_signal_handler(int host_signum, struct siginfo *info,
1351 struct ucontext *uc = puc;
1355 pc = uc->uc_mcontext.psw.addr;
1356 /* XXX: compute is_write */
1358 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1360 &uc->uc_sigmask, puc);
1365 #error host CPU specific signal handler needed
1369 #endif /* !defined(CONFIG_SOFTMMU) */