2 * i386 emulator main execution loop
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include "exec-i386.h"
31 //#define DEBUG_SIGNAL
33 #if defined(TARGET_ARM)
34 /* XXX: unify with i386 target */
35 void cpu_loop_exit(void)
37 longjmp(env->jmp_env, 1);
41 /* main execution loop */
43 int cpu_exec(CPUState *env1)
45 int saved_T0, saved_T1, saved_T2;
74 int code_gen_size, ret;
75 void (*gen_func)(void);
76 TranslationBlock *tb, **ptb;
77 uint8_t *tc_ptr, *cs_base, *pc;
80 /* first we save global registers */
87 /* we also save i7 because longjmp may not restore it */
88 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
91 #if defined(TARGET_I386)
94 EAX = env->regs[R_EAX];
98 ECX = env->regs[R_ECX];
102 EDX = env->regs[R_EDX];
106 EBX = env->regs[R_EBX];
110 ESP = env->regs[R_ESP];
114 EBP = env->regs[R_EBP];
118 ESI = env->regs[R_ESI];
122 EDI = env->regs[R_EDI];
125 /* put eflags in CPU temporary format */
126 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
127 DF = 1 - (2 * ((env->eflags >> 10) & 1));
128 CC_OP = CC_OP_EFLAGS;
129 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
130 #elif defined(TARGET_ARM)
134 env->CF = (psr >> 29) & 1;
135 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
136 env->VF = (psr << 3) & 0x80000000;
137 env->cpsr = psr & ~0xf0000000;
140 #error unsupported target CPU
142 env->interrupt_request = 0;
144 /* prepare setjmp context for exception handling */
145 if (setjmp(env->jmp_env) == 0) {
146 T0 = 0; /* force lookup of first TB */
149 /* g1 can be modified by some libc? functions */
152 if (env->interrupt_request) {
153 env->exception_index = EXCP_INTERRUPT;
158 #if defined(TARGET_I386)
159 /* restore flags in standard format */
160 env->regs[R_EAX] = EAX;
161 env->regs[R_EBX] = EBX;
162 env->regs[R_ECX] = ECX;
163 env->regs[R_EDX] = EDX;
164 env->regs[R_ESI] = ESI;
165 env->regs[R_EDI] = EDI;
166 env->regs[R_EBP] = EBP;
167 env->regs[R_ESP] = ESP;
168 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
169 cpu_x86_dump_state(env, logfile, 0);
170 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
171 #elif defined(TARGET_ARM)
172 cpu_arm_dump_state(env, logfile, 0);
174 #error unsupported target CPU
178 /* we compute the CPU state. We assume it will not
179 change during the whole generated block. */
180 #if defined(TARGET_I386)
181 flags = env->seg_cache[R_CS].seg_32bit << GEN_FLAG_CODE32_SHIFT;
182 flags |= env->seg_cache[R_SS].seg_32bit << GEN_FLAG_SS32_SHIFT;
183 flags |= (((unsigned long)env->seg_cache[R_DS].base |
184 (unsigned long)env->seg_cache[R_ES].base |
185 (unsigned long)env->seg_cache[R_SS].base) != 0) <<
186 GEN_FLAG_ADDSEG_SHIFT;
187 if (!(env->eflags & VM_MASK)) {
188 flags |= (env->segs[R_CS] & 3) << GEN_FLAG_CPL_SHIFT;
190 /* NOTE: a dummy CPL is kept */
191 flags |= (1 << GEN_FLAG_VM_SHIFT);
192 flags |= (3 << GEN_FLAG_CPL_SHIFT);
194 flags |= (env->eflags & (IOPL_MASK | TF_MASK));
195 cs_base = env->seg_cache[R_CS].base;
196 pc = cs_base + env->eip;
197 #elif defined(TARGET_ARM)
200 pc = (uint8_t *)env->regs[15];
202 #error unsupported CPU
204 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
208 /* if no translated code available, then translate it now */
209 tb = tb_alloc((unsigned long)pc);
211 /* flush must be done */
213 /* cannot fail at this point */
214 tb = tb_alloc((unsigned long)pc);
215 /* don't forget to invalidate previous TB info */
216 ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
219 tc_ptr = code_gen_ptr;
221 tb->cs_base = (unsigned long)cs_base;
223 ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
224 #if defined(TARGET_I386)
225 /* XXX: suppress that, this is incorrect */
226 /* if invalid instruction, signal it */
228 /* NOTE: the tb is allocated but not linked, so we
230 spin_unlock(&tb_lock);
231 raise_exception(EXCP06_ILLOP);
235 tb->hash_next = NULL;
237 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
238 spin_unlock(&tb_lock);
242 fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
243 (long)tb->tc_ptr, (long)tb->pc,
244 lookup_symbol((void *)tb->pc));
250 /* see if we can patch the calling TB. XXX: remove TF test */
252 #if defined(TARGET_I386)
253 && !(env->eflags & TF_MASK)
257 tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
258 spin_unlock(&tb_lock);
262 /* execute the generated code */
263 gen_func = (void *)tc_ptr;
264 #if defined(__sparc__)
265 __asm__ __volatile__("call %0\n\t"
269 : "i0", "i1", "i2", "i3", "i4", "i5");
270 #elif defined(__arm__)
271 asm volatile ("mov pc, %0\n\t"
272 ".global exec_loop\n\t"
276 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
282 ret = env->exception_index;
284 #if defined(TARGET_I386)
285 /* restore flags in standard format */
286 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
288 /* restore global registers */
313 #elif defined(TARGET_ARM)
316 ZF = (env->NZF == 0);
317 env->cpsr = env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
318 (env->CF << 29) | ((env->VF & 0x80000000) >> 3);
321 #error unsupported target CPU
324 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
333 void cpu_interrupt(CPUState *s)
335 s->interrupt_request = 1;
339 #if defined(TARGET_I386)
341 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
343 CPUX86State *saved_env;
347 if (env->eflags & VM_MASK) {
350 sc = &env->seg_cache[seg_reg];
351 /* NOTE: in VM86 mode, limit and seg_32bit are never reloaded,
352 so we must load them here */
353 sc->base = (void *)(selector << 4);
356 env->segs[seg_reg] = selector;
358 load_seg(seg_reg, selector, 0);
363 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
365 CPUX86State *saved_env;
370 helper_fsave(ptr, data32);
375 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
377 CPUX86State *saved_env;
382 helper_frstor(ptr, data32);
387 #endif /* TARGET_I386 */
399 #include <sys/ucontext.h>
401 /* 'pc' is the host PC at which the exception was raised. 'address' is
402 the effective address of the memory exception. 'is_write' is 1 if a
403 write caused the exception and otherwise 0'. 'old_set' is the
404 signal set which should be restored */
405 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
406 int is_write, sigset_t *old_set)
408 TranslationBlock *tb;
412 #if defined(DEBUG_SIGNAL)
413 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx wr=%d oldset=0x%08lx\n",
414 pc, address, is_write, *(unsigned long *)old_set);
416 /* XXX: locking issue */
417 if (is_write && page_unprotect(address)) {
422 /* the PC is inside the translated code. It means that we have
423 a virtual CPU fault */
424 ret = cpu_search_pc(tb, &found_pc, pc);
427 #if defined(TARGET_I386)
428 env->eip = found_pc - tb->cs_base;
430 /* we restore the process signal mask as the sigreturn should
431 do it (XXX: use sigsetjmp) */
432 sigprocmask(SIG_SETMASK, old_set, NULL);
433 raise_exception_err(EXCP0E_PAGE, 4 | (is_write << 1));
434 #elif defined(TARGET_ARM)
435 env->regs[15] = found_pc;
438 #error unsupported target CPU
440 /* never comes here */
447 #if defined(__i386__)
449 int cpu_signal_handler(int host_signum, struct siginfo *info,
452 struct ucontext *uc = puc;
459 #define REG_TRAPNO TRAPNO
461 pc = uc->uc_mcontext.gregs[REG_EIP];
462 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
463 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
464 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
468 #elif defined(__powerpc)
470 int cpu_signal_handler(int host_signum, struct siginfo *info,
473 struct ucontext *uc = puc;
474 struct pt_regs *regs = uc->uc_mcontext.regs;
482 if (regs->dsisr & 0x00800000)
485 if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
488 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
489 is_write, &uc->uc_sigmask);
492 #elif defined(__alpha__)
494 int cpu_signal_handler(int host_signum, struct siginfo *info,
497 struct ucontext *uc = puc;
498 uint32_t *pc = uc->uc_mcontext.sc_pc;
502 /* XXX: need kernel patch to get write flag faster */
503 switch (insn >> 26) {
518 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
519 is_write, &uc->uc_sigmask);
521 #elif defined(__sparc__)
523 int cpu_signal_handler(int host_signum, struct siginfo *info,
526 uint32_t *regs = (uint32_t *)(info + 1);
527 void *sigmask = (regs + 20);
532 /* XXX: is there a standard glibc define ? */
534 /* XXX: need kernel patch to get write flag faster */
536 insn = *(uint32_t *)pc;
537 if ((insn >> 30) == 3) {
538 switch((insn >> 19) & 0x3f) {
550 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
554 #elif defined(__arm__)
556 int cpu_signal_handler(int host_signum, struct siginfo *info,
559 struct ucontext *uc = puc;
563 pc = uc->uc_mcontext.gregs[R15];
564 /* XXX: compute is_write */
566 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
573 #error CPU specific signal handler needed