2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env->jmp_env, 1);
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
73 longjmp(env->jmp_env, 1);
77 static TranslationBlock *tb_find_slow(target_ulong pc,
81 TranslationBlock *tb, **ptb1;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
89 tb_invalidated_flag = 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
118 ptb1 = &tb->phys_hash_next;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
131 tc_ptr = code_gen_ptr;
133 tb->cs_base = cs_base;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
144 tb_link_phys(tb, phys_pc, phys_page2);
147 if (tb_invalidated_flag) {
148 /* as some TB could have been invalidated because
149 of memory exceptions while generating the code, we
150 must recompute the hash index here */
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
159 static inline TranslationBlock *tb_find_fast(void)
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
168 #if defined(TARGET_I386)
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 cs_base = env->segs[R_CS].base;
172 pc = cs_base + env->eip;
173 #elif defined(TARGET_ARM)
174 flags = env->thumb | (env->vfp.vec_len << 1)
175 | (env->vfp.vec_stride << 4);
178 #elif defined(TARGET_SPARC)
179 #ifdef TARGET_SPARC64
180 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
182 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
186 #elif defined(TARGET_PPC)
187 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
188 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 #elif defined(TARGET_MIPS)
192 flags = env->hflags & MIPS_HFLAGS_TMASK;
196 #error unsupported CPU
198 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
199 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
200 tb->flags != flags, 0)) {
201 tb = tb_find_slow(pc, cs_base, flags);
207 /* main execution loop */
209 int cpu_exec(CPUState *env1)
211 int saved_T0, saved_T1;
216 #if defined(TARGET_I386)
241 #elif defined(TARGET_SPARC)
242 #if defined(reg_REGWPTR)
243 uint32_t *saved_regwptr;
247 int saved_i7, tmp_T0;
249 int ret, interrupt_request;
250 void (*gen_func)(void);
251 TranslationBlock *tb;
254 cpu_single_env = env1;
256 /* first we save global registers */
265 /* we also save i7 because longjmp may not restore it */
266 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
269 #if defined(TARGET_I386)
296 /* put eflags in CPU temporary format */
297 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
298 DF = 1 - (2 * ((env->eflags >> 10) & 1));
299 CC_OP = CC_OP_EFLAGS;
300 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
301 #elif defined(TARGET_ARM)
305 env->CF = (psr >> 29) & 1;
306 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
307 env->VF = (psr << 3) & 0x80000000;
308 env->QF = (psr >> 27) & 1;
309 env->cpsr = psr & ~CACHED_CPSR_BITS;
311 #elif defined(TARGET_SPARC)
312 #if defined(reg_REGWPTR)
313 saved_regwptr = REGWPTR;
315 #elif defined(TARGET_PPC)
316 #elif defined(TARGET_MIPS)
318 #error unsupported target CPU
320 env->exception_index = -1;
322 /* prepare setjmp context for exception handling */
324 if (setjmp(env->jmp_env) == 0) {
325 env->current_tb = NULL;
326 /* if an exception is pending, we execute it here */
327 if (env->exception_index >= 0) {
328 if (env->exception_index >= EXCP_INTERRUPT) {
329 /* exit request from the cpu execution loop */
330 ret = env->exception_index;
332 } else if (env->user_mode_only) {
333 /* if user mode only, we simulate a fake exception
334 which will be hanlded outside the cpu execution
336 #if defined(TARGET_I386)
337 do_interrupt_user(env->exception_index,
338 env->exception_is_int,
340 env->exception_next_eip);
342 ret = env->exception_index;
345 #if defined(TARGET_I386)
346 /* simulate a real cpu exception. On i386, it can
347 trigger new exceptions, but we do not handle
348 double or triple faults yet. */
349 do_interrupt(env->exception_index,
350 env->exception_is_int,
352 env->exception_next_eip, 0);
353 #elif defined(TARGET_PPC)
355 #elif defined(TARGET_MIPS)
357 #elif defined(TARGET_SPARC)
358 do_interrupt(env->exception_index);
361 env->exception_index = -1;
364 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
366 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
367 ret = kqemu_cpu_exec(env);
368 /* put eflags in CPU temporary format */
369 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
370 DF = 1 - (2 * ((env->eflags >> 10) & 1));
371 CC_OP = CC_OP_EFLAGS;
372 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
375 longjmp(env->jmp_env, 1);
376 } else if (ret == 2) {
377 /* softmmu execution needed */
379 if (env->interrupt_request != 0) {
380 /* hardware interrupt will be executed just after */
382 /* otherwise, we restart */
383 longjmp(env->jmp_env, 1);
389 T0 = 0; /* force lookup of first TB */
392 /* g1 can be modified by some libc? functions */
395 interrupt_request = env->interrupt_request;
396 if (__builtin_expect(interrupt_request, 0)) {
397 #if defined(TARGET_I386)
398 /* if hardware interrupt pending, we execute it */
399 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
400 (env->eflags & IF_MASK) &&
401 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
403 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
404 intno = cpu_get_pic_interrupt(env);
405 if (loglevel & CPU_LOG_TB_IN_ASM) {
406 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
408 do_interrupt(intno, 0, 0, 0, 1);
409 /* ensure that no TB jump will be modified as
410 the program flow was changed */
417 #elif defined(TARGET_PPC)
419 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
424 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
426 env->exception_index = EXCP_EXTERNAL;
429 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
435 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
437 env->exception_index = EXCP_DECR;
440 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
448 #elif defined(TARGET_MIPS)
449 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
450 (env->CP0_Status & (1 << CP0St_IE)) &&
451 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
452 !(env->hflags & MIPS_HFLAG_EXL) &&
453 !(env->hflags & MIPS_HFLAG_ERL) &&
454 !(env->hflags & MIPS_HFLAG_DM)) {
456 env->exception_index = EXCP_EXT_INTERRUPT;
459 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
466 #elif defined(TARGET_SPARC)
467 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
469 int pil = env->interrupt_index & 15;
470 int type = env->interrupt_index & 0xf0;
472 if (((type == TT_EXTINT) &&
473 (pil == 15 || pil > env->psrpil)) ||
475 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
476 do_interrupt(env->interrupt_index);
477 env->interrupt_index = 0;
484 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
485 //do_interrupt(0, 0, 0, 0, 0);
486 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
489 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
490 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
491 /* ensure that no TB jump will be modified as
492 the program flow was changed */
499 if (interrupt_request & CPU_INTERRUPT_EXIT) {
500 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
501 env->exception_index = EXCP_INTERRUPT;
506 if ((loglevel & CPU_LOG_EXEC)) {
507 #if defined(TARGET_I386)
508 /* restore flags in standard format */
510 env->regs[R_EAX] = EAX;
513 env->regs[R_EBX] = EBX;
516 env->regs[R_ECX] = ECX;
519 env->regs[R_EDX] = EDX;
522 env->regs[R_ESI] = ESI;
525 env->regs[R_EDI] = EDI;
528 env->regs[R_EBP] = EBP;
531 env->regs[R_ESP] = ESP;
533 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
534 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
535 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
536 #elif defined(TARGET_ARM)
537 env->cpsr = compute_cpsr();
538 cpu_dump_state(env, logfile, fprintf, 0);
539 env->cpsr &= ~CACHED_CPSR_BITS;
540 #elif defined(TARGET_SPARC)
541 REGWPTR = env->regbase + (env->cwp * 16);
542 env->regwptr = REGWPTR;
543 cpu_dump_state(env, logfile, fprintf, 0);
544 #elif defined(TARGET_PPC)
545 cpu_dump_state(env, logfile, fprintf, 0);
546 #elif defined(TARGET_MIPS)
547 cpu_dump_state(env, logfile, fprintf, 0);
549 #error unsupported target CPU
555 if ((loglevel & CPU_LOG_EXEC)) {
556 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
557 (long)tb->tc_ptr, tb->pc,
558 lookup_symbol(tb->pc));
564 /* see if we can patch the calling TB. When the TB
565 spans two pages, we cannot safely do a direct
569 tb->page_addr[1] == -1
570 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
571 && (tb->cflags & CF_CODE_COPY) ==
572 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
576 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
577 #if defined(USE_CODE_COPY)
578 /* propagates the FP use info */
579 ((TranslationBlock *)(T0 & ~3))->cflags |=
580 (tb->cflags & CF_FP_USED);
582 spin_unlock(&tb_lock);
586 env->current_tb = tb;
587 /* execute the generated code */
588 gen_func = (void *)tc_ptr;
589 #if defined(__sparc__)
590 __asm__ __volatile__("call %0\n\t"
594 : "i0", "i1", "i2", "i3", "i4", "i5");
595 #elif defined(__arm__)
596 asm volatile ("mov pc, %0\n\t"
597 ".global exec_loop\n\t"
601 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
602 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
604 if (!(tb->cflags & CF_CODE_COPY)) {
605 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
606 save_native_fp_state(env);
610 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
611 restore_native_fp_state(env);
613 /* we work with native eflags */
614 CC_SRC = cc_table[CC_OP].compute_all();
615 CC_OP = CC_OP_EFLAGS;
616 asm(".globl exec_loop\n"
621 " fs movl %11, %%eax\n"
622 " andl $0x400, %%eax\n"
623 " fs orl %8, %%eax\n"
626 " fs movl %%esp, %12\n"
627 " fs movl %0, %%eax\n"
628 " fs movl %1, %%ecx\n"
629 " fs movl %2, %%edx\n"
630 " fs movl %3, %%ebx\n"
631 " fs movl %4, %%esp\n"
632 " fs movl %5, %%ebp\n"
633 " fs movl %6, %%esi\n"
634 " fs movl %7, %%edi\n"
637 " fs movl %%esp, %4\n"
638 " fs movl %12, %%esp\n"
639 " fs movl %%eax, %0\n"
640 " fs movl %%ecx, %1\n"
641 " fs movl %%edx, %2\n"
642 " fs movl %%ebx, %3\n"
643 " fs movl %%ebp, %5\n"
644 " fs movl %%esi, %6\n"
645 " fs movl %%edi, %7\n"
648 " movl %%eax, %%ecx\n"
649 " andl $0x400, %%ecx\n"
651 " andl $0x8d5, %%eax\n"
652 " fs movl %%eax, %8\n"
654 " subl %%ecx, %%eax\n"
655 " fs movl %%eax, %11\n"
656 " fs movl %9, %%ebx\n" /* get T0 value */
659 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
660 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
661 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
662 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
663 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
664 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
665 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
666 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
667 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
668 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
670 "m" (*(uint8_t *)offsetof(CPUState, df)),
671 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
676 #elif defined(__ia64)
683 fp.gp = code_gen_buffer + 2 * (1 << 20);
684 (*(void (*)(void)) &fp)();
688 env->current_tb = NULL;
689 /* reset soft MMU for next block (it can currently
690 only be set by a memory fault) */
691 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
692 if (env->hflags & HF_SOFTMMU_MASK) {
693 env->hflags &= ~HF_SOFTMMU_MASK;
694 /* do not allow linking to another block */
705 #if defined(TARGET_I386)
706 #if defined(USE_CODE_COPY)
707 if (env->native_fp_regs) {
708 save_native_fp_state(env);
711 /* restore flags in standard format */
712 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
714 /* restore global registers */
739 #elif defined(TARGET_ARM)
740 env->cpsr = compute_cpsr();
741 /* XXX: Save/restore host fpu exception state?. */
742 #elif defined(TARGET_SPARC)
743 #if defined(reg_REGWPTR)
744 REGWPTR = saved_regwptr;
746 #elif defined(TARGET_PPC)
747 #elif defined(TARGET_MIPS)
749 #error unsupported target CPU
752 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
760 /* fail safe : never use cpu_single_env outside cpu_exec() */
761 cpu_single_env = NULL;
765 /* must only be called from the generated code as an exception can be
767 void tb_invalidate_page_range(target_ulong start, target_ulong end)
769 /* XXX: cannot enable it yet because it yields to MMU exception
770 where NIP != read address on PowerPC */
772 target_ulong phys_addr;
773 phys_addr = get_phys_addr_code(env, start);
774 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
778 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
780 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
782 CPUX86State *saved_env;
786 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
788 cpu_x86_load_seg_cache(env, seg_reg, selector,
789 (selector << 4), 0xffff, 0);
791 load_seg(seg_reg, selector);
796 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
798 CPUX86State *saved_env;
803 helper_fsave((target_ulong)ptr, data32);
808 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
810 CPUX86State *saved_env;
815 helper_frstor((target_ulong)ptr, data32);
820 #endif /* TARGET_I386 */
822 #if !defined(CONFIG_SOFTMMU)
824 #if defined(TARGET_I386)
826 /* 'pc' is the host PC at which the exception was raised. 'address' is
827 the effective address of the memory exception. 'is_write' is 1 if a
828 write caused the exception and otherwise 0'. 'old_set' is the
829 signal set which should be restored */
830 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
831 int is_write, sigset_t *old_set,
834 TranslationBlock *tb;
838 env = cpu_single_env; /* XXX: find a correct solution for multithread */
839 #if defined(DEBUG_SIGNAL)
840 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
841 pc, address, is_write, *(unsigned long *)old_set);
843 /* XXX: locking issue */
844 if (is_write && page_unprotect(address, pc, puc)) {
848 /* see if it is an MMU fault */
849 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
850 ((env->hflags & HF_CPL_MASK) == 3), 0);
852 return 0; /* not an MMU fault */
854 return 1; /* the MMU fault was handled without causing real CPU fault */
855 /* now we have a real cpu fault */
858 /* the PC is inside the translated code. It means that we have
859 a virtual CPU fault */
860 cpu_restore_state(tb, env, pc, puc);
864 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
865 env->eip, env->cr[2], env->error_code);
867 /* we restore the process signal mask as the sigreturn should
868 do it (XXX: use sigsetjmp) */
869 sigprocmask(SIG_SETMASK, old_set, NULL);
870 raise_exception_err(EXCP0E_PAGE, env->error_code);
872 /* activate soft MMU for this block */
873 env->hflags |= HF_SOFTMMU_MASK;
874 cpu_resume_from_signal(env, puc);
876 /* never comes here */
880 #elif defined(TARGET_ARM)
881 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
882 int is_write, sigset_t *old_set,
885 TranslationBlock *tb;
889 env = cpu_single_env; /* XXX: find a correct solution for multithread */
890 #if defined(DEBUG_SIGNAL)
891 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
892 pc, address, is_write, *(unsigned long *)old_set);
894 /* XXX: locking issue */
895 if (is_write && page_unprotect(address, pc, puc)) {
898 /* see if it is an MMU fault */
899 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
901 return 0; /* not an MMU fault */
903 return 1; /* the MMU fault was handled without causing real CPU fault */
904 /* now we have a real cpu fault */
907 /* the PC is inside the translated code. It means that we have
908 a virtual CPU fault */
909 cpu_restore_state(tb, env, pc, puc);
911 /* we restore the process signal mask as the sigreturn should
912 do it (XXX: use sigsetjmp) */
913 sigprocmask(SIG_SETMASK, old_set, NULL);
916 #elif defined(TARGET_SPARC)
917 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
918 int is_write, sigset_t *old_set,
921 TranslationBlock *tb;
925 env = cpu_single_env; /* XXX: find a correct solution for multithread */
926 #if defined(DEBUG_SIGNAL)
927 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
928 pc, address, is_write, *(unsigned long *)old_set);
930 /* XXX: locking issue */
931 if (is_write && page_unprotect(address, pc, puc)) {
934 /* see if it is an MMU fault */
935 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
937 return 0; /* not an MMU fault */
939 return 1; /* the MMU fault was handled without causing real CPU fault */
940 /* now we have a real cpu fault */
943 /* the PC is inside the translated code. It means that we have
944 a virtual CPU fault */
945 cpu_restore_state(tb, env, pc, puc);
947 /* we restore the process signal mask as the sigreturn should
948 do it (XXX: use sigsetjmp) */
949 sigprocmask(SIG_SETMASK, old_set, NULL);
952 #elif defined (TARGET_PPC)
953 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
954 int is_write, sigset_t *old_set,
957 TranslationBlock *tb;
961 env = cpu_single_env; /* XXX: find a correct solution for multithread */
962 #if defined(DEBUG_SIGNAL)
963 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
964 pc, address, is_write, *(unsigned long *)old_set);
966 /* XXX: locking issue */
967 if (is_write && page_unprotect(address, pc, puc)) {
971 /* see if it is an MMU fault */
972 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
974 return 0; /* not an MMU fault */
976 return 1; /* the MMU fault was handled without causing real CPU fault */
978 /* now we have a real cpu fault */
981 /* the PC is inside the translated code. It means that we have
982 a virtual CPU fault */
983 cpu_restore_state(tb, env, pc, puc);
987 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
988 env->nip, env->error_code, tb);
990 /* we restore the process signal mask as the sigreturn should
991 do it (XXX: use sigsetjmp) */
992 sigprocmask(SIG_SETMASK, old_set, NULL);
993 do_raise_exception_err(env->exception_index, env->error_code);
995 /* activate soft MMU for this block */
996 cpu_resume_from_signal(env, puc);
998 /* never comes here */
1002 #elif defined (TARGET_MIPS)
1003 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1004 int is_write, sigset_t *old_set,
1007 TranslationBlock *tb;
1011 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1012 #if defined(DEBUG_SIGNAL)
1013 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1014 pc, address, is_write, *(unsigned long *)old_set);
1016 /* XXX: locking issue */
1017 if (is_write && page_unprotect(address, pc, puc)) {
1021 /* see if it is an MMU fault */
1022 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1024 return 0; /* not an MMU fault */
1026 return 1; /* the MMU fault was handled without causing real CPU fault */
1028 /* now we have a real cpu fault */
1029 tb = tb_find_pc(pc);
1031 /* the PC is inside the translated code. It means that we have
1032 a virtual CPU fault */
1033 cpu_restore_state(tb, env, pc, puc);
1037 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1038 env->nip, env->error_code, tb);
1040 /* we restore the process signal mask as the sigreturn should
1041 do it (XXX: use sigsetjmp) */
1042 sigprocmask(SIG_SETMASK, old_set, NULL);
1043 do_raise_exception_err(env->exception_index, env->error_code);
1045 /* activate soft MMU for this block */
1046 cpu_resume_from_signal(env, puc);
1048 /* never comes here */
1053 #error unsupported target CPU
1056 #if defined(__i386__)
1058 #if defined(USE_CODE_COPY)
1059 static void cpu_send_trap(unsigned long pc, int trap,
1060 struct ucontext *uc)
1062 TranslationBlock *tb;
1065 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1066 /* now we have a real cpu fault */
1067 tb = tb_find_pc(pc);
1069 /* the PC is inside the translated code. It means that we have
1070 a virtual CPU fault */
1071 cpu_restore_state(tb, env, pc, uc);
1073 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1074 raise_exception_err(trap, env->error_code);
1078 int cpu_signal_handler(int host_signum, struct siginfo *info,
1081 struct ucontext *uc = puc;
1089 #define REG_TRAPNO TRAPNO
1091 pc = uc->uc_mcontext.gregs[REG_EIP];
1092 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1093 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1094 if (trapno == 0x00 || trapno == 0x05) {
1095 /* send division by zero or bound exception */
1096 cpu_send_trap(pc, trapno, uc);
1100 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1102 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1103 &uc->uc_sigmask, puc);
1106 #elif defined(__x86_64__)
1108 int cpu_signal_handler(int host_signum, struct siginfo *info,
1111 struct ucontext *uc = puc;
1114 pc = uc->uc_mcontext.gregs[REG_RIP];
1115 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1116 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1117 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1118 &uc->uc_sigmask, puc);
1121 #elif defined(__powerpc__)
1123 /***********************************************************************
1124 * signal context platform-specific definitions
1128 /* All Registers access - only for local access */
1129 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1130 /* Gpr Registers access */
1131 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1132 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1133 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1134 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1135 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1136 # define LR_sig(context) REG_sig(link, context) /* Link register */
1137 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1138 /* Float Registers access */
1139 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1140 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1141 /* Exception Registers access */
1142 # define DAR_sig(context) REG_sig(dar, context)
1143 # define DSISR_sig(context) REG_sig(dsisr, context)
1144 # define TRAP_sig(context) REG_sig(trap, context)
1148 # include <sys/ucontext.h>
1149 typedef struct ucontext SIGCONTEXT;
1150 /* All Registers access - only for local access */
1151 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1152 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1153 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1154 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1155 /* Gpr Registers access */
1156 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1157 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1158 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1159 # define CTR_sig(context) REG_sig(ctr, context)
1160 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1161 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1162 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1163 /* Float Registers access */
1164 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1165 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1166 /* Exception Registers access */
1167 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1168 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1169 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1170 #endif /* __APPLE__ */
1172 int cpu_signal_handler(int host_signum, struct siginfo *info,
1175 struct ucontext *uc = puc;
1183 if (DSISR_sig(uc) & 0x00800000)
1186 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1189 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1190 is_write, &uc->uc_sigmask, puc);
1193 #elif defined(__alpha__)
1195 int cpu_signal_handler(int host_signum, struct siginfo *info,
1198 struct ucontext *uc = puc;
1199 uint32_t *pc = uc->uc_mcontext.sc_pc;
1200 uint32_t insn = *pc;
1203 /* XXX: need kernel patch to get write flag faster */
1204 switch (insn >> 26) {
1219 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1220 is_write, &uc->uc_sigmask, puc);
1222 #elif defined(__sparc__)
1224 int cpu_signal_handler(int host_signum, struct siginfo *info,
1227 uint32_t *regs = (uint32_t *)(info + 1);
1228 void *sigmask = (regs + 20);
1233 /* XXX: is there a standard glibc define ? */
1235 /* XXX: need kernel patch to get write flag faster */
1237 insn = *(uint32_t *)pc;
1238 if ((insn >> 30) == 3) {
1239 switch((insn >> 19) & 0x3f) {
1251 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1252 is_write, sigmask, NULL);
1255 #elif defined(__arm__)
1257 int cpu_signal_handler(int host_signum, struct siginfo *info,
1260 struct ucontext *uc = puc;
1264 pc = uc->uc_mcontext.gregs[R15];
1265 /* XXX: compute is_write */
1267 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1272 #elif defined(__mc68000)
1274 int cpu_signal_handler(int host_signum, struct siginfo *info,
1277 struct ucontext *uc = puc;
1281 pc = uc->uc_mcontext.gregs[16];
1282 /* XXX: compute is_write */
1284 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1286 &uc->uc_sigmask, puc);
1289 #elif defined(__ia64)
1292 /* This ought to be in <bits/siginfo.h>... */
1293 # define __ISR_VALID 1
1294 # define si_flags _sifields._sigfault._si_pad0
1297 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1299 struct ucontext *uc = puc;
1303 ip = uc->uc_mcontext.sc_ip;
1304 switch (host_signum) {
1310 if (info->si_code && (info->si_flags & __ISR_VALID))
1311 /* ISR.W (write-access) is bit 33: */
1312 is_write = (info->si_isr >> 33) & 1;
1318 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1320 &uc->uc_sigmask, puc);
1323 #elif defined(__s390__)
1325 int cpu_signal_handler(int host_signum, struct siginfo *info,
1328 struct ucontext *uc = puc;
1332 pc = uc->uc_mcontext.psw.addr;
1333 /* XXX: compute is_write */
1335 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1337 &uc->uc_sigmask, puc);
1342 #error host CPU specific signal handler needed
1346 #endif /* !defined(CONFIG_SOFTMMU) */