more cleanup

diff --git a/cpu.cpp b/cpu.cpp
index 7727a0c..2ab337e 100644 (file)
--- a/cpu.cpp
+++ b/cpu.cpp
@@ -61,7 +61,7 @@
 
 extern struct FxInit_s SuperFX;
 
-void S9xResetSuperFX ()
+static void S9xResetSuperFX ()
 {
     SuperFX.vFlags = 0; //FX_FLAG_ROM_BUFFER;// | FX_FLAG_ADDRESS_CHECKING;
     FxReset (&SuperFX);

diff --git a/fxinst.cpp b/fxinst.cpp
index 54c300c..fe12de1 100644 (file)
--- a/fxinst.cpp
+++ b/fxinst.cpp
@@ -1564,16 +1564,17 @@ static void fx_sm_r15() { FX_SM(15); }
 
 static uint32 fx_run(uint32 nInstructions)
 {
-    GSU.vCounter = nInstructions;
-    READR14;
-    while(GSU.vCounter-- > 0)
-       FX_STEP;
+       GSU.vCounter = nInstructions;
+       READR14;
+       while(GSU.vCounter-- > 0) {
+               FX_STEP;
+       }
  /*
 #ifndef FX_ADDRESS_CHECK
     GSU.vPipeAdr = USEX16(R15-1) | (USEX8(GSU.vPrgBankReg)<<16);
 #endif
 */
-    return (nInstructions - GSU.vInstCount);
+       return nInstructions - GSU.vInstCount;
 }
 
 static uint32 fx_run_to_breakpoint(uint32 nInstructions)

diff --git a/fxinst.h b/fxinst.h
index 01d4163..d682a80 100644 (file)
--- a/fxinst.h
+++ b/fxinst.h
@@ -386,8 +386,11 @@ struct FxRegs_s
 #define CLSR USEX8(GSU.pvRegisters[GSU_CLSR])
 
 /* Execute instruction from the pipe, and fetch next byte to the pipe */
-#define FX_STEP { uint32 vOpcode = (uint32)PIPE; FETCHPIPE; \
-(*fx_ppfOpcodeTable[ (GSU.vStatusReg & 0x300) | vOpcode ])(); } \
+#define FX_STEP { \
+       uint32 vOpcode = (uint32)PIPE; \
+       FETCHPIPE; \
+       (*fx_ppfOpcodeTable[ (GSU.vStatusReg & 0x300) | vOpcode ])(); \
+} \
 
 #define FX_FUNCTION_RUN                        0
 #define FX_FUNCTION_RUN_TO_BREAKPOINT  1

diff --git a/os9x_65c816.s b/os9x_65c816.s
index ad72c44..30aba8f 100644 (file)
--- a/os9x_65c816.s
+++ b/os9x_65c816.s
@@ -579,7 +579,6 @@ reg_cpu_var .req R14
 .endif
 .endm
 
-@ #include "os9x_65c816_mac_mem.h"
 .macro         S9xGetWord      
                @  in  : rscratch (0x00hhmmll)
                @  out : rscratch (0xhhll0000)
@@ -2865,7 +2864,7 @@ SW_not_aligned4:
 1111:
 .endm
 .macro         Op30    /*BMI*/
-               asmRelative             
+               asmRelative
                BranchCheck0
                TST             rstatus, #MASK_NEG
                BEQ             1111f
@@ -3087,15 +3086,14 @@ SW_not_aligned4:
 .endm
 .macro         OpAB
                BIC             reg_d_bank,reg_d_bank, #0xFF
-               PullBrS         
+               PullBrS
                ORR             reg_d_bank,reg_d_bank,rscratch, LSR #24
                UPDATE_ZN
                ADD2CYCLE
 .endm
-.macro         Op2B            
-               BIC             reg_d,reg_d, #0xFF000000
-               BIC             reg_d,reg_d, #0x00FF0000
-               PullWrS         
+.macro         Op2B
+               UXTH    reg_d,reg_d
+               PullWrS
                ORR             reg_d,rscratch,reg_d
                UPDATE_ZN
                ADD2CYCLE